Patents Assigned to Intel Corporations
  • Patent number: 12160216
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a heat source on the substrate, and a heat pipe. The heat pipe includes a plurality of bumps that extend from the heat pipe towards the substrate but do not come into contact with the substrate. The bumps are configured to help mitigate radio frequency interference in the electronic device. More specifically, the bumps can be configured to provide a resonant frequency in a specific radio frequency band and act as a radio frequency filter.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Kae-An Liu, Jaejin Lee, David W. Browning
  • Patent number: 12159353
    Abstract: While many augmented reality systems provide “see-through” transparent or translucent displays upon which to project virtual objects, many virtual reality systems instead employ opaque, enclosed screens. Indeed, eliminating the user's perception of the real-world may be integral to some successful virtual reality experiences. Thus, head mounted displays designed exclusively for virtual reality experiences may not be easily repurposed to capture significant portions of the augmented reality market. Various of the disclosed embodiments facilitate the repurposing of a virtual reality device for augmented reality use. Particularly, by anticipating user head motion, embodiments may facilitate scene renderings better aligned with user expectations than naïve renderings generated within the enclosed field of view. In some embodiments, the system may use procedural mapping methods to generate a virtual model of the environment. The system may then use this model to supplement the anticipatory rendering.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 3, 2024
    Assignee: INTEL CORPORATION
    Inventors: Anna Petrovskaya, Peter Varvak
  • Patent number: 12159844
    Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Benjamin Duong, Roy Dittler, Darko Grujicic, Chandrasekharan Nair, Rengarajan Shanmugam
  • Patent number: 12159813
    Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
  • Patent number: 12159825
    Abstract: An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Rahul Manepalli, Suddhasattwa Nad, Marcel Wall, Darko Grujicic
  • Patent number: 12158852
    Abstract: Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Robert Pawlowski, Bharadwaj Krishnamurthy, Shruti Sharma, Byoungchan Oh, Jing Fang, Daniel Klowden, Jason Howard, Joshua Fryman
  • Patent number: 12160971
    Abstract: An apparatus is described. The apparatus includes an electronic component to be plugged into an electronic system. The electronic component includes a housing. The housing includes a jam. The jam is to push through a first opening in a bottom of the housing and a second opening in a surface when the first and second openings are at least partially aligned. The surface is a mechanical component of the electronic system that the electrical component is to slide upon when being plugged into the electronic system. The jam includes tooth edges to engage with an edge of the second opening.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Kristin L. Weldon, Barrett M. Faneuf
  • Patent number: 12160369
    Abstract: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Chih-Jen Chang, Daniel Christian Biederman, Matthew James Webb, Wing Cheung, Jose Niell, Robert Hathaway
  • Patent number: 12158625
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a bidirectional optical grating coupler that may be used for testing. A photonic apparatus includes a first layer with electro-optical circuitry that is optically coupled with a bidirectional optical grating coupler. A second layer is physically coupled with a first side of the first layer and includes a first light path to optically coupled with the bidirectional optical grating coupler. A third layer is physically coupled with a second side of the first layer opposite the first side of the first layer, and includes a second light path that optically couples with the bidirectional grating coupler. Operational testing of the electro-optical circuitry is based in part on light received or transmitted through the second light path. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Kaveh Hosseini, Xiaoqian Li, Conor O'Keeffe, Jing Fang, Kevin P. Ma, Shamsul Abedin
  • Publication number: 20240395655
    Abstract: In one embodiment, an integrated circuit package includes a package substrate, a first integrated circuit die electrically coupled to the package substrate via wire bond connectors, and a second integrated circuit die coupled to the package substrate. The package further includes a heat spreader coupled to the first integrated circuit die via a thermal interface material (TIM) and a dielectric material encompassing the first integrated circuit die and the second integrated circuit die on the package substrate. A top surface of the heat spreader is aligned with a top surface of the dielectric material.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Avi Tsarfati, David T. O’Sullivan, Vishnu Prasad, Thomas Wagner, Aruna Manoharan
  • Publication number: 20240396852
    Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark A. Schmisseur, Timothy Verrall
  • Publication number: 20240395567
    Abstract: Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Jonas G. Croissant, Yiqun Bai, Dingying Xu, Xavier F. Brun, Timothy Gosselin, Ye Seul Nam, Gustavo Arturo Beltran, Roberto Serna, Jesus S. Nieto Pescador, Aris Mercado Orbase
  • Publication number: 20240394316
    Abstract: Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Nirmit Parikh, Tanmay Hiren Desai
  • Publication number: 20240393848
    Abstract: A circuit system includes a platform baseboard, an integrated circuit coupled to the platform baseboard, and an auxiliary control board mounted on the platform baseboard. The auxiliary control board includes an interface device that is in communication with the integrated circuit through the platform baseboard. The auxiliary control board can perform power sequencing functions for the circuit system. The auxiliary control board can also perform telemetry gathering, hardware security functions, and configuration of the integrated circuit.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventor: Allen Chan
  • Publication number: 20240396980
    Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.
    Type: Application
    Filed: August 2, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Daniel Daly, John Fastabend, Matthew Vick, Brian J. Skerry, Marco Varlese, Jing Mark Chen, Danny Y. Zhou
  • Publication number: 20240395722
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Publication number: 20240395800
    Abstract: An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of negative current.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Krzysztof Domanski, Harshit Dhakad
  • Publication number: 20240394119
    Abstract: Systems, apparatuses and methods may provide for technology that detects a tensor operation in an application, wherein the tensor operation has an unspecified tensor input size, determines the input tensor size at runtime, and selects a partition configuration for the tensor operation based at least in part on the input tensor size and one or more runtime conditions. In one example, the technology searches a lookup table for the input tensor size and at least one of the runtime condition(s) to select the partition configuration.
    Type: Application
    Filed: August 5, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Sara Baghsorkhi, Mohammad Reza Haghighat
  • Publication number: 20240396711
    Abstract: An accelerator includes a memory, a compute zone to receive an encrypted workload downloaded from a tenant application running in a virtual machine on a host computing system attached to the accelerator, and a processor subsystem to execute a cryptographic key exchange protocol with the tenant application to derive a session key for the compute zone and to program the session key into the compute zone. The compute zone is to decrypt the encrypted workload using the session key, receive an encrypted data stream from the tenant application, decrypt the encrypted data stream using the session key, and process the decrypted data stream by executing the workload to produce metadata.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Akshay Kadam, Sivakumar B, Lawrence Booth, JR., Niraj Gupta, Steven Tu, Ricardo Becker, Subba Mungara, Tuyet-Trang Piel, Mitul Shah, Raynald Lim, Mihai Bogdan Bucsa, Cliodhna Ni Scanaill, Roman Zubarev, Dmitry Budnikov, Lingyun Zhu, Yi Qian, Stewart Taylor
  • Publication number: 20240396327
    Abstract: An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of positive current.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Krzysztof Domanski, Harshit Dhakad