Abstract: Damping structures in integrated circuit (IC) devices, and techniques for forming the structures are discussed. An IC device includes, between an IC package and a socket, both a spring force and a damping structure adjacent an array of pins and corresponding lands. The damping structure may be of a dissipative, viscous, or viscoelastic material. The damping structure may be between the IC package and socket. The damping structure may be within a periphery of the socket. The damping structure may be coupled to the IC package or the socket by an adhesive or a press fit. A heatsink or a heat spreader may be coupled to the IC package over the socket.

Abstract: For example, a debug target may include an interconnect interface; and a debug manager configured to cause the debug target to process a debug request message received from a Debug and Test System (DTS) via the interconnect interface. For example, the debug request message may include a group Identifier (ID) value and a debug request. For example, the debug manager may be configured to cause the debug target to execute the debug request, for example, based on a determination that the group ID value is to identify a group of debug targets including the debug target. For example, the debug manager may be configured to cause the debug target to send a debug response message via the interconnect interface, the debug response message including the group ID value and a debug response for the DTS.

Abstract: Techniques and mechanisms for circuitry to support the performance of a fused multiply-add (FMA) operation with one or more denormal numbers. In some embodiments, a processor is operable to execute a FMA instruction comprising or otherwise identifying two multiplicands, and an addend. Such execution includes performing one-way alignment of an addend significand based on a difference between respective exponent values of the two multiplicands. The alignment is performed in parallel with operations by a multiplier circuit based on respective significand values of the two multiplicands. Subtraction of a J-bit correction value is performed in the multiplier circuit to avoid mitigate execution delay. In another embodiment, first circuitry of a processor executes an FMA instruction, wherein components of the first circuitry are shared with second circuitry of the processor, and wherein the second circuitry supports the execution of a floating-point multiplication instruction.

Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

Abstract: Aerogel including low thermal conductivity gases and related apparatus and methods are disclosed. An example aerogel disclosed herein includes a framework including a plurality of pores and a gas in at least one of the plurality of pores, the gas having a lower thermal conductivity than air.

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Abstract: Techniques for implementing instructions and modified instruction encodings for checking tags and for interspersing islands of tags in line with bucketed data for locality by a processor are described. In an example, an apparatus includes decoder circuitry and execution circuitry. The decoder circuitry is to decode an instruction into a decoded instruction. The instruction has an opcode to indicate that the execution circuitry is to use metadata and instruction encodings to selectively perform a memory safety check. The execution circuitry is to execute the decoded instruction according to the opcode.

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.

Abstract: Methods, systems, and apparatus described herein relate to a conformable cold plate for fluid cooling applications. An example method includes re-shaping a tube to contour non-uniform surfaces; and assembling a fluid cooling assembly using the re-shaped tube, the re-shaped tube capable to transfer fluid for cooling of one or more devices.

Abstract: Systems, apparatus, articles of manufacture, and methods to reduce stress between sockets and associated integrated circuit packages having glass cores are disclosed. An example integrated circuit package includes: a semiconductor die, and a substrate including a glass core. The substrate includes a first surface, a second surface opposite the first surface, and a third surface between the first surface and the second surfaces. The first surface supports the semiconductor die. The second surface includes first contacts to electrical couple with second contacts in a socket. At least a portion of the third surface separated and distinct from the glass core.

Abstract: For example, an apparatus may include logic and circuitry configured to cause a sensing initiator station (STA) to transmit one or more timeslot-scheduling frames over a sub 10 Gigahertz (GHz) (sub-10 GHz) wireless communication frequency band to schedule one or more timeslots of a coordinated monostatic millimeterWave (mmWave) sensing measurement exchange for a plurality of sensing responder STAs; to transmit a trigger frame over an mmWave wireless communication frequency band during a timeslot of the one or more timeslots; and to process a frame from a sensing responder STA to participate in a monostatic sounding during the timeslot, the frame from the sensing responder STA received over the mmWave wireless communication frequency band during the timeslot.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Abstract: A machine-readable storage medium, an apparatus and a method, each corresponding to either a service consumer or a service producer of a non-real-time (non-RT) radio access network intelligent controller (RIC) of a Service Management and Orchestration Framework (SMO FW). Communications from the service consumer to the service producer include: a training request for artificial intelligence/machine learning (AI/ML) training job; a query regarding a training status of the AI/ML training job; a cancel training request to cancel the AI/ML training job; and a notification regarding the training status of the AI/ML training job.

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

Abstract: Methods, systems, and use cases for geofence-based edge service control and authentication are discussed, including an orchestration system with memory and at least one processing circuitry coupled to the memory. The processing circuitry is configured to perform operations to obtain, from a plurality of connectivity nodes providing edge services, physical location information, and resource availability information associated with each of the plurality of connectivity nodes. An edge-to-edge location graph (ELG) is generated based on the physical location information and the resource availability information, the ELG indicating a subset of the plurality of connectivity nodes that are available for executing a plurality of services associated with an edge workload. The connectivity nodes are provisioned with the ELG and a workflow execution plan to execute the plurality of services, the workflow execution plan including metadata with a geofence policy.

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.