Patents Assigned to Intel Corporations
  • Patent number: 12120312
    Abstract: Techniques related to quantization parameter estimation for coding intra and scene change frames are discussed. Such techniques include generating features based on an intra or scene change frame including a proportion of smooth blocks and one or both of a measure of block variance and a prediction distortion, and applying a machine learning model to generate an estimated quantization parameter for encoding the intra or scene change frame.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Sang-hee Lee, Keith W. Rowe
  • Patent number: 12120012
    Abstract: A device of a service coordinating entity includes communications circuitry to communicate with a plurality of access networks via a corresponding plurality of network function virtualization (NFV) instances, processing circuitry, and a memory device. The processing circuitry is to perform operations to monitor stored performance metrics for the plurality of NFV instances. Each of the NFV instances is instantiated by a corresponding scheduler of a plurality of schedulers on a virtualization infrastructure of the service coordinating entity. A plurality of stored threshold metrics is retrieved, indicating a desired level for each of the plurality of performance metrics. A threshold condition is detected for at least one of the performance metrics for an NF V instance of the plurality of NFV instances, based on the retrieved plurality of threshold metrics. A hardware resource used by the NFV instance to communicate with an access network is adjusted based on the detected threshold condition.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Andrew J. Herdrich, Karthik Kumar, Felipe Pastor Beneyto, Edwin Verplanke, Rashmin Patel, Monica Kenguva, Brinda Ganesh, Alexander Vul, Ned M. Smith
  • Patent number: 12116013
    Abstract: A system for a distributed in-vehicle real-time sensor data processing can be adapted to receive a request for sensor data from vehicles. The system may be further adapted to generate an application for collection of the sensor data. The application may have sensor requirements for performing the collection of sensor data. The system may be further adapted to identify a set of vehicles for distribution of the application based on available sensors in each vehicle corresponding to the sensor requirements. The system may be further adapted to transmit the application to the set of vehicles and receive sensor data results from respective instances of the application executing on the set of vehicles. The system may be further adapted to transmit a command to remove the respective instances of the application from the set of vehicles.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Cornelius Buerkle, Kay-Ulrich Scholl, Fabian Oboril, Frederik Pasch
  • Patent number: 12119409
    Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
  • Patent number: 12117908
    Abstract: Systems, apparatuses and methods may provide for technology that associates a unique identifier with an application, creates an entry in a metadata table, wherein the metadata table is at a fixed location in persistent system memory, populates the entry with the unique identifier, a user identifier, and a pointer to a root of a page table tree, and recovers in-use data pages after a system crash. In one example, the in-use data pages are recovered from the persistent system memory based on the metadata table and include one or more of application heap information or application stack information.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Aravinda Prasad, Sreenivas Subramoney
  • Patent number: 12117910
    Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Nrupal Jani, Manasi Deval, Anjali Singhai Jain, Parthasarathy Sarangam, Mitu Aggarwal, Neerav Parikh, Alexander H. Duyck, Kiran Patil, Rajesh M. Sankaran, Sanjay K. Kumar, Utkarsh Y. Kakaiya, Philip Lantz, Kun Tian
  • Patent number: 12120595
    Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Stephen T. Palermo, Chetan Hiremath, Rajesh Gadiyar, Jason K. Smith, Valerie J. Parker, Udayan Mukherjee, Neelam Chandwani, Francesc Guim Bernat, Ned M. Smith
  • Patent number: 12118756
    Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: October 15, 2024
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
  • Patent number: 12120550
    Abstract: Various systems and methods for improving connectivity of a Mobility-as-a-Service (MaaS) node are described herein, including categorizing MaaS communication traffic of a MaaS node into different levels of priority and controlling duplication or repetition of the MaaS communication traffic using the categorized level of priority of the MaaS communication traffic.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Satish Chandra Jha, S M Iftekharul Alam, Ned M. Smith, Vesh Raj Sharma Banjade, Xiaoyun May Wu, Ignacio Javier Alvarez Martinez, Arvind Merwaday, Kuilin Clark Chen
  • Patent number: 12119326
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Bohan Shan
  • Patent number: 12118775
    Abstract: Methods, systems and apparatuses may provide for technology that detects an individual in a real-time multi-camera video feed and generates three-dimensional (3D) skeletal data based on the real-time multi-camera video feed. The technology may also automatically identify a frontal body orientation of an individual based on the 3D skeletal data and one or more anthropometric constraints.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Qiang Li, Wenlong Li, Yumeng Wang, Xiaofeng Tong
  • Patent number: 12118654
    Abstract: One embodiment provides a graphics processor comprising an interface to a system interconnect and a graphics processor coupled to the interface, the graphics processor comprising circuitry configured to compact sample data for multiple sample locations of a pixel, map the multiple sample locations to memory locations that store compacted sample data, the memory locations in a memory of the graphics processor, apply lossless compression to the compacted sample data, and update a compression control surface associated with the memory locations, the compression control surface to specify a compression status for the memory locations.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Prasoonkumar Surti, Joydeep Ray, Michael J. Norris
  • Patent number: 12117878
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to reduce display connection latency. An example apparatus includes interface circuitry to: detect when a display is plugged into a port; and notify processor circuitry of the detection. In response to the notification, the processor circuitry of the example apparatus moves discrete circuitry into a high power state. The example apparatus also includes discrete circuitry to, while in the high power state, identify the display.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 15, 2024
    Assignee: INTEL CORPORATION
    Inventors: Lakshminarayana Pappu, Nausheen Ansari, Todd Witter
  • Publication number: 20240338558
    Abstract: The disclosure relates to adaptive buffer management to support a dynamic tensor shape in a DNN. An apparatus for the DNN may include processor circuitry configured to: determine whether a tensor shape of an input tensor of an object in the DNN is dynamic and exists in a shape buffer pool; run the object by use of a compilation result for the object stored in the shape buffer pool when the tensor shape of the input tensor is dynamic and exists in the shape buffer pool; and invoke the compilation procedure to perform JIT compilation for the object so as to get the compilation result for the object when the tensor shape of the input tensor is dynamic and does not exist in the shape buffer pool.
    Type: Application
    Filed: December 6, 2021
    Publication date: October 10, 2024
    Applicant: Intel Corporation
    Inventor: Liyang LING
  • Publication number: 20240339410
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid, Randy B. Osborne, Van H. Le
  • Publication number: 20240337692
    Abstract: A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Applicant: Intel Corporation
    Inventors: Rajiv Kumar, Amit Agarwal, Steven Hsu, Scott Weber
  • Publication number: 20240338319
    Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Applicant: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Ashok Raj, Kun Tian
  • Publication number: 20240338238
    Abstract: A method and system of host to guest (H2G) notification are disclosed. H2G is provided via an instruction. The instruction is a send user inter-processor interrupt instruction. An exemplary processor includes decoder circuitry to decode a single instruction and execute the decoded single instruction according to the at least the opcode to cause a host to guest notification from a virtual device running in a host machine on the first physical processor to a virtual device driver running on a virtual processor in a guest machine on a second physical processor.
    Type: Application
    Filed: January 26, 2022
    Publication date: October 10, 2024
    Applicant: Intel Corporation
    Inventors: Wei Wang, Kun Tian, Guang Zeng, Gilbert Neiger, Rajesh Sankaran, Asit Mallick, Jr-Shian Tsai, Jacob Jun Pan, Mesut Ergin
  • Patent number: 12113117
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 12113868
    Abstract: Methods, systems, and storage media for accessing one or more services provided by one or more detected Internet of Things (“IoT”) devices are described. In embodiments, a mobile device may detect a plurality of IoT devices, obtain an identifier for each of the plurality of IoT devices based on the detection, and obtain an indicator for each of the plurality of IoT devices based at least in part on a corresponding one of the obtained identifiers, wherein each indicator may indicate a service type of a corresponding one of the plurality of IoT devices. The mobile device may generate a notification that indicates a plurality of services available to the mobile device based on each of the obtained indicators. The mobile device may access a service of the plurality of services, wherein the access may include utilization of a set of the plurality of IoT devices required to provide the service. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Edward Wang, Richard Chow