Abstract: According to one embodiment, a communication device is described comprising a first determiner configured to determine a signal transmission time between the communication device and another communication device, wherein the communication device and the other communication device have a communication session with each other and communication resources are allocated for exchanging data in course of the communication session; a second determiner configured to determine a waiting period based on the determined signal transmission time; a transmitter configured to transmit a message indicating that the communication session is to be ended; and a controller configured to control the communication device to release the communication resources when the waiting period has elapsed since the transmitting of the message by the transmitter.

Abstract: A signal processing device for providing first and second analog signals includes first and second clocked digital signal path circuits and a transit time difference measuring device. The first clocked digital signal path circuit is configured to yield first digital data for providing a first analog signal. The second clocked digital signal path circuit is configured to yield second digital data for providing the second analog signal. The transit time difference measuring device is configured to yield a transit time difference measuring signal describing a difference between a signal transit time along a first measuring path and a signal transit time along a second measuring path, with the first measuring path including a first clock supply allocated to the first clocked digital signal path circuit, and with the second measuring path including a second clock supply allocated to the second clocked digital signal path circuit.

Abstract: One embodiment of the present invention relates to a level shifter circuit having switchable current mirrors that can be selectively activated and deactivated in a complementary manner to translate differential input signals between logic sides (e.g., to translate a differential input signal received at a low-side to a high-side). A latch is connected to outputs of the switchable current mirrors. The latch is configured to receive a translated output signal from an activated current mirror and drive the other output signal to a complementary value. The latch is also configured to provide the translated output signal to a switching element that deactivates (e.g., turns off) the activated switchable current mirror. Storage of the output signals allows for the current mirrors to remain deactivated until a new input signal is provided to the level shifter circuit, thereby allowing for a reduction in the static power consumption of the level shifter.

Abstract: One embodiment of the present invention relates to a power amplifier comprising a plurality of amplifying elements connected in a serial-parallel matrix configuration, containing parallel columns having amplifying elements connected in series. The parallel columns are connected to a common output path coupled to a supply voltage source configured to provide an equal supply voltage to each of the columns. One or more input signals (e.g., RF input signals) are connected to the power amplifier by way of input terminals on a first row of amplifying elements. The remaining amplifying elements have control terminals that are connected to independent control signals, which allow each amplifying element to be operated independent of the other amplifying elements in the matrix. This selective operation of amplifying elements allows for improved efficiency over a wide range of power amplifier output powers.

Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Abstract: Disclosed herein are techniques, systems, and methods relating maintaining a time base between receiving and transmitting assemblies during interruption of data streams communicated therebetween.

Abstract: This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.

Abstract: A diversity receiver includes a plurality of receiver circuits that are configured to receive and process the received radio frequency signals. A channel estimator is coupled to at least one of the plurality of receiver circuits and is configured to determine at least one channel estimation value for the received radio frequency signals. A controller is coupled to the channel estimator and to at least one of the plurality of receiver circuits and is configured to selectively activate or deactivate the at least one of the plurality of receiver circuits based on the determined at least one channel estimation value.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: In a method for transmitting a channel quality information on the quality of a communication channel in a radio communications system the system includes a regular cycle for transmitting the channel quality information in an uplink direction from a communication unit to a network, and the method including suppressing in the communication unit the transmitting of the channel quality information based on a predefined condition.

Abstract: A method for computer-aided mapping of system information medium access control protocol messages onto a plurality of transport channels for transmission using an orthogonal frequency division multiple access method, wherein a scheduling of system information data packets information in the context of the mapping on a transport channel of the plurality of transport channels is carried out dependent on the type of the system information.

Abstract: According to one embodiment, a communication terminal is provided comprising a transceiver configured to transmit data in accordance with a plurality of transmission processes wherein each transmission process may be activated or deactivated, a receiver configured to receive a message including a message field which specifies a number of transmission processes to which a request for transmission process activation or deactivation is to be applied and a controller configured to activate or deactivate the number of transmission processes in accordance with the request.

Abstract: An apparatus and methods for a baseband modulator configured to code amplitude signals into pulse width modulated time signals comprising at least two amplitude levels is disclosed. A pulse width modulator can receive a component signal of a baseband complex signal and generate a discrete-time pulse width modulated signal. This signal can be converted to a continuous time signal, such as a pulse-width modulated time signal and can be shifted to a carrier signal corresponding respectively to the component signal by a switch. Bursts sequences are generated to an input of a switched amplifier for driving operation of the amplifier therein.

Abstract: A method for data transmission is provided for determining movement speed and/or location of a mobile communication device; selecting, based on the movement speed and/or the location of the mobile communication device a frequency hopping mode from a plurality of frequency hopping modes to be used for data transmission to or from the mobile communication device; and transmitting the data using the selected frequency hopping mode.

Abstract: One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies.

Abstract: A modulation device includes a signal input for receiving a data stream to be modulated and a first and a second signal output. At least one first complex component is derived from the data stream in a coding device. A first and a second high-frequency signal are output via the signal outputs. The first and second high-frequency signals are derived from the at least one first complex component and are distinguished by the fact that the second high-frequency signal has a phase shift of substantially 90° with respect to the first high-frequency signal.

Abstract: A method for controlling a transmit power in a radio communications system includes receiving a request to increase a transmit power of an uplink channel and determining whether the transmit power was at a maximum upon receipt of a previous request to increase the transmit power preceding the received request. If the transmit power was not at the maximum upon receipt of the previous request, the transmit power is increased by a first step size and if the transmit power was at the maximum upon receipt of the previous request, the transmit power is increased by a second step size greater than the first step size.

Abstract: A transmit circuit includes a power amplifier configured to amplify an RF input signal to obtain an RF output signal, and an antenna tuner configured to transform an antenna impedance to an impedance at an input of the antenna tuner, wherein the input of the antenna tuner is coupled to an output of the power amplifier. The transmit circuit further includes a bias controller configured to control a bias of the power amplifier, wherein the bias controller is configured to provide a bias control signal to adjust the bias of the power amplifier based on a determination of a measure of a load impedance provided to the power amplifier by the antenna tuner.

Abstract: A network selection device is described comprising a determining circuit configured to determine an expected suitability level of a communication connection for a communication terminal provided by means of a cellular radio communication network and by means of a relaying subscriber terminal of the cellular radio communication network and a decider configured to decide, based on the determined expected suitability level, whether the communication terminal should use a communication connection provided by means of the cellular radio communication network and by means of the relaying subscriber terminal of the cellular radio communication network.

Abstract: A radio communication device may be provided. The radio communication device may include: a first circuit; a second circuit; a processor configured to operate the radio communication device in a plurality of operation modes, wherein the plurality of operation modes may include: a first operation mode in which the first circuit processes received data of a first communication channel independent from the second circuit and in which the second circuit processes received data of a second communication channel independent from the first circuit; and a second operation mode in which the first circuit and the second circuit jointly process received data of a third communication channel. The radio communication device may further include a mode switching circuit configured to switch between the plurality of operation modes.