Abstract: According to one embodiment, a mobile communication device is provided comprising a determiner configured to determine at least one of a geographical position of the mobile communication device within a first mobile radio cell in which the mobile communication device is located and a movement direction of the mobile communication device; a selector configured to select, based on at least one of the determined geographical position and the determined movement direction, from a plurality of second mobile radio cells at least one second mobile radio cell for a radio link performance measurement (RLPM); and a measuring circuit configured to measure the performance of a radio link between the mobile communication device and a base station operating the at least one selected second mobile radio cell.

Abstract: According to an embodiment, a determining device for determining a transmission parameter for wirelessly transmitting energy (414) from a sending device (402) to a receiving apparatus (401) is provided, comprising: an authorization checking device which is configured to carry out an authorization (403, 404, 405, 406) in order to determine whether the receiving apparatus is authorized to receive energy from the sending device, a sending/receiving apparatus which is configured to send and receive messages (409, 410, 411) during a message exchange with the receiving apparatus in order to determine the transmission parameter (413); and a parameter determining device which is configured to determine the transmission parameter (413) based on the authorization and based on the message exchange, if the receiving apparatus is authorized to receive energy from the sending device.

Abstract: A method for decoding a wireless channel includes generating hypotheses of how many antennas each of at least two base stations have in a synchronized network and how received signals are being transmitted for each of the at least two base stations, detecting a MIMO signal using the hypotheses and signal components received from the at least two base stations, decoding the signal, and determining whether the decoded signal is valid by performing a cyclical redundancy check calculation.

Abstract: An apparatus for providing a linearity information associated with an amplifier includes an operating state determinator and an evaluator. The operating state determinator is configured to obtain information describing a gain of the amplifier for at least one bias condition of the amplifier. The evaluator is configured to obtain the linearity information based on both the information describing the gain of the amplifier and information about the at least one bias condition of the amplifier using a gain-bias characteristic of the amplifier. A bias circuit including the apparatus for providing the linearity information is also disclosed.

Abstract: A method, system, and computer program product for identifying network congestion in a communication system. A connection manager identifies a number of packet delay times of a plurality of data packets within the communication system; determines whether the at least one packet delay time meets a threshold; and responsive to the at least one packet delay time meeting the threshold, adjusts a congestion indicator.

Abstract: A method of accessing a physical random access channel, a method of signaling access information for accessing a physical random access channel, a mobile communication terminal and a base station are provided. The method of accessing a physical random access channel comprises selecting a plurality of transmission time intervals from transmission time intervals being allowed for accessing a physical random access channel, randomly selecting one transmission time interval of the plurality of transmission time intervals, and accessing the physical random access channel in the randomly selected transmission time interval. A mobile communication terminal is configured to carry out the method.

Abstract: A system for simplifying message sequences is disclosed. The system includes a shrink component and a message simplification component. The shrink component is configured to receive a failure inducing message sequence and to provide a shrunk sequence based on the failure inducing message sequence. The shrunk sequence has less or equal number of messages than the failure inducing message sequence. The message simplification component is configured to receive the shrunk sequence and to simplify messages within the shrunk sequence to generate a simplified message sequence including debugging hints.

Abstract: A method comprises predicting a workload required for decoding a code block using a turbo decoder and selecting a power mode of the turbo decoder, the selection of the power mode depending on the prediction of the workload.

Abstract: A multi user receiver configured to receive a signal including multiple symbol streams assigned to various users is described. The multiple symbol streams include at least one first symbol stream assigned to a user of the multi user receiver and at least one second symbol stream assigned to another user, wherein a modulation alphabet applied for the at least one second symbol stream is unknown at the multi user receiver. The multi user receiver includes a symbol stream election unit configured to elect a symbol stream of the multiple symbol streams, an equalizer configured to provide an equalized symbol of the elected symbol stream, and a detector configured to generate a detected symbol from the equalized symbol on the basis of a constellation, wherein, if the second symbol stream is elected, the constellation is a mixed constellation including constellation points of at least two of multiple predefined modulation alphabets.

Abstract: An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

Abstract: A receiver includes a first amplifier and a second amplifier, a first mixer, a second mixer and a third mixer, a first baseband signal path and a second baseband signal path. A signal output of the first amplifier is coupled to a signal input of the first mixer and a signal input of the second mixer. A signal output of the second amplifier is coupled to a signal input of the third mixer. A signal output of the first mixer and a signal output of the third mixer are coupled to the first baseband signal path. A signal output of the second mixer is coupled to the second baseband signal path.

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of capacitors, a first input for a clock signal, a second input for a phase shift clock signal and an output. The phase interpolator is configured to provide an interpolated, modulated phase information signal by switching, dependent on a modulation information, a first number of the capacitors between the first input and the output and a second number of the capacitors between the second input and the output.

Abstract: One embodiment of the present invention relates to a method and apparatus are provided herein for reducing the power consumption of a transmission chain while maintaining an acceptable figure of merit (e.g., linearity). In one embodiment, an adaptive biasing element is configured to perform adaptive biasing to reduce current consumption of a transmission chain by adjusting the operating point of one or more transmission chain elements (e.g., power amplifier, mixer, etc.). However, since adaptive biasing may reduce the linearity of a transmitted signal, its use is limited by the degradation of figure of merit caused by the introduced non-linearities. Accordingly, a pre-distortion element may be configured to perform adaptive digital pre-distortion (DPD) on a transmission chain input signal to account for non-linearities generated through the adaptive biasing, therefore allowing the adaptive biasing to further reduce the current consumption while maintaining an acceptable figure of merit.

Abstract: An adjustable delayer for adjustably delaying an input signal based on a delay adjustment input information describing a desired delay includes a plurality of series-connected tunable delay circuits, wherein a first of the tunable delay circuits is configured to receive the input signal. The adjustable delayer also includes a closed-loop control circuit configured to provide a first delay tuning information to tune a combined delay of the plurality of tunable delay circuits to fulfill a predetermined condition. The adjustable delayer also includes a combiner to combine the first delay tuning information with a second delay tuning information, that is based on the delay adjustment input information, to obtain a combined delay tuning information. The adjustable delayer is configured to tune a delay of one or more of the tunable delay circuits based on the combined delay tuning information.

Abstract: A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient.

Abstract: A chip arrangement may include: a first chip including a first contact, a second contact, and a redistribution structure electrically coupling the first contact to the second contact; a second chip including a contact; and a plurality of interconnects electrically coupled to the second contact of the first chip, wherein at least one interconnect of the plurality of interconnects electrically couples the second contact of the first chip to the contact of the second chip.

Abstract: A method, system, and computer program product for managing noise in a noise reduction system, comprising: receiving a first signal at a first microphone; receiving a second signal at a second microphone; identifying noise estimation in the first signal and the second signal; identifying a transfer function of the noise reduction system using a ratio of a power spectral density of the second signal minus the noise estimation to a power spectral density of the first signal, wherein the noise estimation is removed from only the power spectral density of the second signal; and identifying a gain of the noise reduction system using the transfer function.

Abstract: An amplifier includes an amplifying stage configured to provide an amplifier output signal based on a combination of a received amplifying stage input signal and a received amplified version of the amplifying stage input signal.

Abstract: A ROM memory circuit is disclosed having at least one electrical line, at least one keeper circuit electrically connected to the at least one electrical line, the keeper circuit including a first transistor, a terminal of the first transistor is driven by a dedicated control signal, wherein the dedicated control signal is configured to keep the voltage of the at least one electrical line at a first voltage.

Abstract: An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of logical elements and a bus carrying signals for said plurality of logical elements. The integrated circuit also comprises a routing unit having an input coupled to said bus and a plurality of outputs to route signals received at said input to at least one of said outputs. The integrated circuit also comprises a plurality of lines coupled to said plurality of outputs to conduct said signals from said routing unit to at least one of said plurality of logical elements, wherein at least one of said plurality of lines couples said routing unit to only one of said logical elements.