Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.

Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

Abstract: Methods and apparatus for fast and efficient verify recovery and array discharge for 3D NAND memory arrays and other 3D storage devices. The 3D storage device includes storage arrays including strings of memory cells stacked on top of one another and sharing a channel in a pillar for the string. The memory cells for a string occupy respective tiers in a 3D structure with each tier having an associated wordline. A controller is used to program charge levels in the memory cells. Programming is followed by a fast verify recovery where a voltage is applied to the wordlines to perform a program verify, followed by discharging wordlines. Erased wordlines are identified and discharged first, followed by programmed wordlines, which may employ staggered discharge sequences. Dummy wordlines are then discharged, with an optional timer delay. For multi-deck devices, wordlines in the deck with an active wordline are discharged before wordlines in one or more other decks.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Abstract: A ring oscillator (RO) circuit for capturing one or more characteristics relating to aging of CMOS circuitry in a CMOS device has been described. The RO circuit includes a plurality of stages coupled via an RO feedback signal line and forming an inverter chain. The plurality of stages include, for each stage, a respective CMOS inverter comprising a pair of pMOS and nMOS transistors followed by a pass gate, wherein an output of a pass gate for a stage is coupled to an input for the respective CMOS inverter of a next stage. The plurality of stages include an enable stage to enable the inverter chain to be put into a free oscillating mode or another mode in which the RO circuit does not freely oscillate. The plurality of stages include a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and pre-stage are isolated from one another.

Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that issues a program pulse to a selected subblock of a NAND memory array, conducts a pulse recovery phase after the program pulse, and shuts down unselected subblocks in the NAND memory array during the pulse recovery phase.

Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally on a step of the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and an etch stop material formed around the wordline contact and on the polysilicon wordline, where the etch stop material extends to an outside corner of the step, the etch stop material is absent from a sidewall of the step, and the etch stop material is undercut at the outside corner of the step. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

Abstract: An embodiment of an apparatus may include a chuck body, and a surface formed on the chuck body to hold a wafer, where the surface has a non-flat shape. Other embodiments are disclosed and claimed.

Abstract: The gap width in a threshold voltage (Vt) distribution for a 3D NAND Flash cell is improved by performing touchup program on a selected portion of the word lines in a block after all of the word lines in the block have been programmed.

Abstract: An apparatus, a method and a system. The apparatus comprises a memory array including word lines defining a staircase structure, and a staircase etch stop layer including: a sandwich etch stop layer disposed on a top region the staircase and including a first etch stop layer and a third etch stop layer of a first material, and a second etch stop layer sandwiched between the first etch stop layer and the third etch stop layer and made of a second material having etch properties different from the first material; a precut etch stop layer disposed at a region of the staircase structure below the top region and including the second etch stop layer and the third etch stop layer and not the first etch stop layer; and contact structures extending through a dielectric layer and the staircase etch stop layer and landing on the word lines at the staircase structure.

Abstract: An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.

Abstract: NAND performance is increased by reducing the time to perform program operations. An operation to program a portion of NAND cells in a NAND memory array includes multiple stages. NAND performance is increased by reducing the time in a first stage of the multiple stages to compute parameters that are used in a second stage to perform program operation(s) and verify operation(s). The time in the first stage is reduced by enabling dynamic prologue selection to dynamically select one of multiple sets of first stage operations to be performed in the first stage for a program operation based on the Word Line (WL), WL-Group, and block information for a current program operation and a previous program operation.

Abstract: Methods for fabricating interconnect arrangements of a metallization layer Mx by using stitching that is enabled by subtractive metallization are disclosed. An example method includes providing a metal layer and a collection layer over the metal layer. The method then includes forming openings for two sets of metal lines by performing a first lithographic process to provide, in the collection layer, first openings for a first set of lines, and then performing a second lithographic process to provide, in the collection layer, second openings for a second set of lines. The method further includes performing a third lithographic process to provide a further opening (a stitch opening) that overlaps with at least one of the first openings of a first track and at least one of the second openings of a second track, and, finally, transferring the pattern of the first, second, and stitch openings to the metal layer.

Abstract: A semiconductor circuit includes multiple decks of semiconductor devices, each deck having multiple three-dimensional (3D) stacks. The semiconductor circuit has a nitride layer between the first deck and the second deck. The nitride layer has a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck. The nitride layer can have multiple sublayers, with a mirrored gradient doping, with lower doping toward the middle of the nitride layer and higher doping toward the outsides of the nitride layer that interfaces with the decks.

Abstract: Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.

Abstract: A memory device with a three-dimensional (3D) staircase memory stack includes dummy connectors proximate semi-isolated connectors. The memory device includes multiple wordlines stacked in a 3D staircase stack, which includes a wordline at an edge of a region of the staircase. The memory device includes vertical connectors through an isolation layer on the 3D staircase stack to connect the wordlines with conductive lines in an access layer. A wordline at the edge of the region of the staircase has a vertical connector that will be adjacent a connector on one side and not on the other side. The memory device includes at least one dummy vertical connector on the edge side of the vertical connector of the wordline on the edge, wherein the dummy vertical connector does not electrically connect a wordline of the 3D staircase stack to a conductive line in the access layer.

Abstract: Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.