Abstract: A semiconductor circuit includes multiple decks of semiconductor devices, each deck having multiple three-dimensional (3D) stacks. The semiconductor circuit has a nitride layer between the first deck and the second deck. The nitride layer has a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck. The nitride layer can have multiple sublayers, with a mirrored gradient doping, with lower doping toward the middle of the nitride layer and higher doping toward the outsides of the nitride layer that interfaces with the decks.

Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to control access to the NAND memory as two or more groups of memory cells, provide independent operations for the two or more groups of memory cells, share a voltage regulator among at least two of the two or more groups of memory cells, and provide a target constant voltage from the shared voltage regulator to a target group of the two or more groups of memory cells in an independent operation for the target group. Other examples are disclosed and claimed.

Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to provide duty cycle correction (DCC) for one or more write paths of the NAND memory. Other examples are disclosed and claimed.

Abstract: Systems, apparatuses, and methods may provide for technology for forming a gate polysilicon for 3D-NAND complementary metal-oxide semiconductor under array (CuA) on a substrate with a barrier and spacer structure. For example, the technology includes forming a titanium nitride (TiN) barrier adjacent the gate polysilicon and forming a silicon nitride (SiN) spacer around the polysilicon gate and the titanium nitride barrier.