Patents Assigned to Interconnect Portfolio, LLC
  • Multi-surface contact IC packaging structures and assemblies
    Patent number: 7732904
    Abstract: A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: June 8, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy, William F. Wiedemann
  • Interconnect System without Through-Holes
    Publication number: 20100127402
    Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 27, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Kevin P. Grundy, Joseph C. Fjelstad, Gary Yasumura, William F. Wiedemann, Para K. Segaram
  • Electrical Interconnection Devices Incorporating Redundant Contact Points for Reducing Capacitive Stubs and Improved Signal Integrity
    Publication number: 20100112829
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Application
    Filed: January 4, 2010
    Publication date: May 6, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Gary Yasamura, Joseph C. Fjelstad, Kevin P. Grundy, William F. Wiedemann, Matthew J. Stepovich
  • Low profile discrete electronic components and applications of same
    Patent number: 7701323
    Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: April 20, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, William F. Wiedemann, Thomas J. Obenhuber, Inessa Obenhuber, legal representative
  • High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture
    Patent number: 7651336
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram, Kevin P. Grundy
  • Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity
    Patent number: 7651382
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, Kevin P. Grundy, William F. Wiedemann, Matthew J. Stepovich
  • Interconnect system without through-holes
    Patent number: 7652381
    Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Kevin P. Grundy, Joseph C. Fjelstad, Gary Yasumura, William F. Wiedemann, Para K. Segaram
  • Signal-segregating connector system
    Patent number: 7613011
    Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 3, 2009
    Assignee: Interconnect Portfolio LLC
    Inventors: Kevin P. Grundy, Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram
  • Controlled Impedance Structures for High Density Interconnections
    Publication number: 20090167334
    Abstract: An interconnection structure suitable for use as an IC package, probe head or other electrical termination of high density where uninterrupted controlled impedance is desired is described.
    Type: Application
    Filed: January 2, 2009
    Publication date: July 2, 2009
    Applicant: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy
  • Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity
    Patent number: 7404746
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: July 29, 2008
    Assignee: Interconnect Portfolio, LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, Kevin P. Grundy, William F. Wiedemann, Matthew J. Stepovich
  • Tapered dielectric and conductor structures and applications thereof
    Patent number: 7388279
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 17, 2008
    Assignee: Interconnect Portfolio, LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Gary Yasumura