Abstract: A method, apparatus, and article of manufacture for interfacing queryable datastore persistent objects to non-relational, non-object-oriented datastores. A computerized system in accordance with the principles of the present invention includes a "bridge" for receiving a request to access a datastore persistent object stored, for retrieving a logical unit of data from the external non-object-oriented datastore in response to the request, and for populating the datastore persistent object with the logical unit of data retrieved from the external non-object-oriented datastore, so that the logical unit of data is encapsulated within the datastore persistent object.

Abstract: A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure.

Abstract: A zoned sequential track format is shown and described which reduces the number of head switches during disk drive read/write operations. A band of selected tracks that form a data recording zone or a portion of such a zone are organized into an odd number of track sequences with each sequence being resident on a single disk surface. In the embodiment of a drive with an even number of data surfaces, the tracks within the band on one surface are partitioned to form two track sequences. This can readily be accomplished using 2-cylinder skipping to have each sequence contain alternate tracks across the band. By having each track sequence accessed during a generally radial passage of the transducer over the band, the odd number of track sequences causes the transducers to be adjacent the next successive band when the last track sequence of the current band has been accessed. Incrementing between bands is effected by an access between tracks on the same data surface.

Abstract: The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

Abstract: An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

Abstract: A test socket is provided as part of a high temperature electromigration test system to allow the prediction of median time to failure to temperatures in excess of 450.degree. C. of VSLI interconnects.

Abstract: A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

Abstract: A composition for cleaning solder to remove flux, flux reaction products, residues, including residues from manufacturing operations such as plating and photoresist residues and other contaminants, without any significant dissolution of the solder especially solder used in fabricating electronic components such as C4 area array flip chip connectors, is provided. The composition comprises a non-aromatic sulfonic acid and a substituted alcohol with a preferred composition comprising 3 weight % methanesulfonic acid and 97 weight % trifluoroethanol. A method for cleaning solder and solder containing components made using the cleaning method and composition of the invention are also disclosed.

Abstract: A transaction manager intercepts all requests for service from any of a plurality of clients, establishes connections independently of task requests and assigns available servers to the requests in the order the requests are received in order to provide equitable distribution of service resources over an increased number of client/server connections. Preferably, the transaction manager provides for starting at least one server independently of any request, direction of all client requests for server connections to a transaction manager independently of any server, placement of task requests in a queue and starting and stopping additional servers based on queue length.

Abstract: A method of determining bias or overlay error in a substrate formed by a lithographic process uses a pair of straight vernier arrays of parallel elements, a staggered vernier array of parallel elements, and optionally at least one image shortening array on the substrate. The ends of the elements form the array edges. The vernier arrays are overlaid such that: i) the elements of the straight and staggered arrays are substantially parallel; ii) one of the edges of the staggered array intersects with one of the edges of one the straight arrays; and iii) the other of the edges of the staggered array intersects with one of the edges of the other of the straight arrays.

Abstract: An improved particle lens has an axis that is shifted to follow the central ray of the beam as it is deflected through the lens creating, in effect, a variable curvilinear optical axis for the lens and introducing aberrations having depending on the object size and the distance off the lens symmetry axis. These aberrations are corrected by a set of correction elements generating compensating aberrations of the same type, comprising at least one wire pair perpendicular to the system axis and carrying fixed currents to introduce a gradient in the field, together with three coils centered on the system axis to cancel a bias field introduced by the wire pair.

Abstract: A single furnace loading cycle technique and a ventable sintering box therefor are disclosed for the sintering of products, such as, ceramic substrates. The sintering box includes a closeable cover which is held open by collapsible or deformable or sensitive spacers in a first furnace temperature range. The sensitive spacers collapse or deform in a higher temperature range to seal closed the box and the substrates therein. Thus, volatile agents within the substrates are permitted to escape in the first temperature range but are prevented from escaping in the higher temperature range.Provision also is made using additional sensitive spacers for applying a weight upon the substrates when in the higher temperature range due to the collapse or deformation of the sensitive spacers.

Abstract: A print bias target is imaged in a single layer of light-sensitive material. The print bias target is made up of a pair of concentric geometric shapes in which a plurality of target regions forms a plurality of isolated edges. Each target region is of a different image structure than each other target region immediately adjacent thereto. The positioning of a given isolated edge in the print bias target is determined relative to a corresponding isolated edge in the design image from which the print bias target was imaged. Focus setting and/or exposure setting for a lithographic system to minimize print bias may be determined using print bias information obtained from a print bias target matrix of varying exposure and focus. An imaging aberration may also be identified using print bias information from a print bias target matrix, such as lithographic astigmatism, lithographic coma and vibration.

Abstract: A computer implemented method incrementally updates a design placement in a very large scale integrated (VLSI) chip. A data structure is generated which defines a chosen specification and initial placement of circuits is input to a computer aided design (CAD) system. The CAD system divides a design area into placement cells. Local constraint values and limits are computed and changes made in the design specification. Replacement regions are then identified, expanded, and replaced. Constraint values are recomputed and the steps of the method are repeated until no more changes are required.

Abstract: A method and system are provided for executing a service processor request within a data processing system having one or more processors within a central processing complex, each of the processors within the central processing complex including allocatable processor resources. Each of the processors within the central processing complex is provided with the capability of processing selected service processor requests by reserving a portion of the allocatable processor resources within each of the processors for such purpose. A service processor request within the central processing complex is initially processed utilizing at least one of the processors in response to receiving a service processor request, if sufficient processor resources are available to process the service processor request within the reserved portion of the allocatable resources.

Abstract: A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.

Abstract: A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.

Abstract: A direct access storage device (DASD) includes a plurality of motion limiters and/or a continuous motion limiter projecting from at least one of the base and cover, each motion limiter having faces disposed in close proximity to and confronting opposite surfaces of a data storage disk adjacent a peripheral portion of the disk that does not contain data. Preferably, the motion limiters are disposed at several points about the periphery of the disk, and may be incorporated in a load/unload ramp and/or side rails of the DASD. The faces of the motion limiters are disposed relative to the disk so that when the DASD is subjected to an acceleration, the disk contacts at least one of the faces only at the peripheral portion of the disk, outside the data zone. Accordingly, the motion limiters prevent data zone and spindle bearing damage when the DASD is dropped.

Abstract: According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock.

Abstract: The present invention accommodates, in an integrated suspension assembly for a magnetic disk storage system, tolerances in the lead and slider position in a manner to maintain gimbal integrity, minimize static attitude variation and reduce stress build up in the lead. In one aspect of the present invention, the nominal lead position and slider position are chosen such that the distance between them in an overlapping interference manner is no more than (a+b), the sum of the extreme tolerance a of the lead position and extreme tolerance b of the slider position. This is to ensure at least line to line contact between the slider and the leads, in an interference type contact configuration. In another aspect of the present invention, the ends of the leads are coated with a layer of solder material which can be reflowed to form a solder joint bonding the contacting leads to the slider.