Abstract: The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.

Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

Abstract: A method, processor architecture, computer program product, and data processing system for determining when an instruction in a pipelined processor should be completed is provided. As each instruction is issued to an execution unit, an entry for that instruction is placed within a “finish pipe,” which consists of a series of consecutively numbered stages. Each clock cycle, the entries in the finish pipe advance one stage. When an entry has reached the stage corresponding to the latency of its associated execution unit, it becomes mature. Each clock cycle, the finish pipe is scanned to find the entry having the highest-numbered stage of any entry in the finish pipe. If that entry is mature, it is removed from the finish pipe and the instructions associated with that entry is allowed to complete. If not, the entry simply advances along with the other entries and the pipe rescanned in the next cycle.

Abstract: The method for controlling a computer that notifies an operating system of a request event corresponding to a device event from hardware. A device event may be generated, for example by a user operating a keyboard or mouse connected to the computer. That is, the device event occurs when a certain event is provided to the hardware of the computer. A request event causes a process corresponding to the device event to be performed under the control of an operating system. Then a response event from the operating system caused by the notification of the request event is accepted and a process event corresponding to the accepted response event is output to the hardware.

Abstract: A timer management system and method for managing timers in both a synchronous and asynchronous system. In one embodiment of the present invention, a timer management system comprises an application program interface (API) for providing a set of synchronous functions allowing an application to functionally operate on the timer. The timer management system further comprises a timer database for storing timer-related information. Furthermore, the timer management system comprises a timer services for detecting the expiring of the timer. A handle function of the timer services allows an asynchronous application, i.e., application in a multi-task system, to synchronously act on the timer. That is, when a timer in a asynchronous system times-out, the handle function allows the asynchronous application to act on the expired timer without incurring an illegal time-out message.

Abstract: The invention provides methods and apparatus for substrate inspection and other lighting applications. It includes an lighting apparatus 10 which comprises: an illuminator 12 including a light source for emitting lights 14; supporting means for supporting an object (e.g. a patterned substrate) 18 having a finely patterned surface 16 on which predetermined patterns are formed, which is illuminated at a predetermined angle with the lights 14 from the illuminator 12; and determining means 24 for determining whether or not predetermined patterns on the surface of the object (substrate) 16 are deformed using lights 22 diffracted by the finely patterned surface 16, wherein the illuminator 12 applies two kinds of lights 14 each having a narrow wavelength range with a peak wavelength at a respective one of two complementary colors.

Abstract: A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design.

Abstract: An improved data structure handles locks and other mutual exclusion (mutex) mechanisms during a “panic” shutdown of the system such as when the system “hangs”. Existing mutex data structures include an identifier of the engine/processor, the thread, or the processes acquiring the mutex. The improved mutex data structure further includes an indicator of whether the mutex was acquired before or after the panic (pre-panic or post-panic), preferably as a modification of the engineID after the panic is initiated such as by assigning the engines different engineIDs post-panic. The method checks mutexes to determine whether they were acquired pre- or post-panic mutexes. During a panic, alternative mutex handling routines free (release) pre-panic mutexes and shoot down the processors owning these mutexes. The data structure and method are generally useful in state transitions of the system, its engines/processors, and its processes and threads.

Abstract: A connector for twisted pair cables used to transmit high frequency data signals. The conductors of the twisted pair are connected to contact blades by an auto-latching mechanism adapted to ensure contact with the corresponding contact blades of a mating connector. Each contact blade has constant thickness but has an initial width in its rectilinear part and a narrower second width in the portion where contact is made with the corresponding portion of the contact blade of the other connector, such that the common mode impedance is the same in the rectilinear part and in the portion where the contact takes place.

Abstract: A system for estimating the bandwidth of a baseband filter that produces a phase shift on arriving analog signals is disclosed. The system comprises means for generating a digital reference clock signal and means for converting the digital reference clock signal into an analog reference clock signal to be input to the baseband filter. Phase comparison means are coupled to the baseband filter for comparing the digital reference clock signal to the analog reference clock signal phase shifted through the baseband filter. A digital pulsed signal that is representative of the phase shift is generated, and digital circuit means connected to the phase comparison means convert the digital pulsed signal into a digital value, the digital value being proportional to the phase shift of the baseband filter.

Abstract: A symmetric multiprocessor data processing system having a highly scalable shared cache memory hierarchy is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units includes a level one cache memory. All the level one cache memories are associated with a level two cache memory. The level two cache memory is non-inclusive of all the level one cache memories. An invalidation bus is connected to all of the level one cache memories. In response to a write access to a specific cache line within one of the level one cache memories, the invalidation bus invalidates other cache lines that shared identical information with the specific cache line within the rest of the level one cache memories.

Abstract: A system and apparatus to couple a bracket member with a receiver member is disclosed. Embodiments may couple bracket members with receiver members, such as brackets to rails of racks, via a flexible member. The flexible member may secure a bracket member to a receiver member by fastening the bracket member to a corresponding extension or tab of the receiver member. Some embodiments may load a second portion of the flexible member such that pressure applied to the second portion can transfer the load to a first portion of the flexible member to facilitate coupling the bracket member with or decoupling the bracket member from the receiver member. In many of these embodiments, the load may transfer as a waveform along the flexible member. Further embodiments provide a lever for the second portion of the flexible member to facilitate transferring a load to the first portion.

Abstract: A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

Abstract: An optimization technique for SQL queries, a program storage device storing the optimization program, and an apparatus for optimizing a query is provided. A query is analyzed to determine whether it includes subselect expressions that return exactly or at most one tuple. If so, the quantifier merger or elimination is performed, if possible, to allow query to perform more efficiently than that of the original query while providing same results. The query is then executed in the computer to efficiently retrieve data from the database.

Abstract: A TFT array substrate 10 of the present invention includes an insulating substrate 12, thin-film transistors formed on the insulating substrate 12 in a matrix, and wirings 46 electrically connected to the thin-film-transistors. A gate-insulating film 32 is formed on the wiring 46, a passivation film 38 is formed on the gate-insulating film 32, and moreover an interlayer insulating film 42 containing an organic polymer with an edge formed thereon is formed on the gate-insulating film 32. An etching stopper 50 is formed on at least either of the gate-insulating film 32 exposed from the edge 48 of the interlayer insulating film 42 or the passivation film 38.

Abstract: A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.

Abstract: An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.

Abstract: An apparatus, program product and method use a congestion relief algorithm in connection with automated buffer insertion to relieve potential congestion during post-layout interconnect routing. The congestion relief algorithm is utilized to manipulate a plurality of L-shaped spans defined in a routing tree, and is configured to apply the congestion relief algorithm to at least a first L-shaped span among the plurality of L-shaped spans by rerouting the first L-shaped span at least partially within a rectangular area bounded by the first L-shaped span.