Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.

Abstract: An apparatus for optical coupling comprises a substrate, a first waveguide formed on the substrate and includes a grating structure directing light in a first direction, and a second waveguide formed on the first waveguide and including an angled portion directing the light in a second direction different from the first direction.

Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Abstract: An apparatus for controlling an electric motor is provided. A plurality of switches is provided for controlling a direction of current through motor coils of the electric motor. A brushless motor control circuit is connected to each of the plurality of switches. Responsive to a request to adjust one of an angular velocity and an angular acceleration of the electric motor, the plurality of switches are activated to place the motor coils in a predetermined configuration to maximize torque or reduce a total back electromotive force (BEMF) from the motor coils.

Abstract: Provided are a computer program product, system, and method for replicating tracks from a first storage to a second and third storages. A determination is made of a track in the first storage to transfer to the second storage as part of a point-in-time copy relationship and of a stride of tracks including the target track. The stride of tracks including the target track is staged from the first storage to a cache according to the point-in-time copy relationship. The staged stride is destaged from the cache to the second storage. The stride in the cache is transferred to the third storage as part of a mirror copy relationship. The stride of tracks in the cache is demoted in response to destaging the stride of the tracks in the cache to the second storage and transferring the stride of tracks in the cache to the third storage.

Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

Abstract: Serializer-deserializer (SERDES) and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate. The first and second SERDES dies positioned adjacent, in a plane, and disposed on the package substrate. The logic circuit communicatively connected to the SERDES circuit and to the package substrate. The logic die stacked vertically and disposed on the first and second SERDES dies. A method of assembling a SERDES and integrated circuit package including providing a SERDES structure selected from a menu of SERDES die and SERDES circuit combinations. A design structure of a SERDES and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate.

Abstract: A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin. The first set of disposable semiconductor material portions is replaced with a first set of active semiconductor regions by a combination of an etch and a selective epitaxy process that deposits a first semiconductor material. A second dielectric liner is deposited and patterned to form openings above the second set of disposable semiconductor material portions. The second set of disposable semiconductor material portions is replaced with a second set of active semiconductor regions employing another epitaxy process that deposits a second semiconductor material. The active semiconductor regions can have the same faceting profile irrespective of the semiconductor materials therein.

Abstract: Improving wafer-to-wafer bonding alignment. Determining planar distortions of the bonding surface of a host wafer. Mounting a donor wafer on a bonding chuck by a plurality of fixation points, the bonding chuck including multiple zones capable of movement relative to each other. Distorting the bonding surface of the donor wafer by moving the zones of the bonding chuck relative to each other to cause distortions of the bonding surface of the donor wafer such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface.

Abstract: A method of tracking and collecting solar energy includes receiving solar energy on at least two solar energy receivers, measuring an energy output from each of the at least two solar energy receivers, comparing the energy output from one of the at least two solar energy receiver with the energy output from another of the at least two solar energy receivers, and shifting the at least two solar energy receivers until the energy output from the one of the at least two solar receivers is substantially equal to the another of the at least two solar receivers.

Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.

Abstract: A mechanism is provided for transmitting a multicast session to a plurality of receivers over a wireless network. A forward error correction (FEC) overhead and a transmission rate are determined for transmission of a next data block of the multicast session based on received channel conditions. The next data block is multicast using the determined FEC overhead and transmission rate. Responsive to an indication of common missing packets from the next data block from more than one receiver in the plurality of receivers, the common missing packets are multicast to the plurality of receivers using the determined FEC overhead and transmission rate. Responsive to an indication of uncommon missing packets from the data block from one or more receivers, for each receiver in the one or more receivers, the uncommon missing packets identified by the receiver are unicast using the determined FEC overhead and transmission rate.

Abstract: A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing an oxide layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.

Abstract: Methods for fabricating device structures, such as bipolar transistors and diodes. The method includes forming a trench extending through stacked semiconductor and insulator layers and into an underlying semiconductor substrate. The trench may be at least partially filled with a sacrificial plug containing a dopant with a conductivity type opposite to the conductivity type of the semiconductor substrate. Dopant is transported outwardly from the sacrificial plug into the semiconductor substrate surrounding the trench to define a doped region of the second conductivity type in the semiconductor substrate. A first contact is formed that extends through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region. A second contact is formed that extends through the semiconductor and insulator layers to the doped region.

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract: A method, apparatus and program product for allocating resources in a logically partitioned multiprocessor environment. Resource usage is monitored in a first logical partition in the logically partitioned multiprocessor environment to predict a future underutilization of a resource in the first logical partition. An application executing in a second logical partition in the logically partitioned multiprocessor environment is configured for execution in the second logical partition with an assumption made that at least a portion of the underutilized resource is allocated to the second logical partition during at least a portion of the predicted future underutilization of the resource.

Abstract: Provided is a method for protecting a thermal sensitive component mounted on a board during a thermal process. The method includes: providing the board, providing a protection apparatus which is removable and made of a thermoelectric material to protect the thermal sensitive component during the thermal process, wherein the protection apparatus cools the thermal sensitive component during the thermal process in response to applying a voltage to the protection apparatus. Further provided is the protection apparatus for the thermal sensitive component mounted on the board during the thermal process.

Abstract: A mechanism is provided for handling incidents occurring in a managed environment. An incident is detected in a resource in the managed environment. A set of incident handling actions are identified based on incident handling rules for an incident type of the incident. From the set of incident handling actions, one incident handling action is identified to be executed based on a set of impact indicators associated with the set of incident handling rules. The identified incident handling action is then executed to address the failure of the resource.