Abstract: A mechanism for routing content, e.g., an electronic document, an invention disclosure, etc., to a person or group of persons, e.g., a reviewer/review team, for review and evaluation of the electronic document. This mechanism involves receiving the content and analyzing the content to generate identifiers of subject matter of the content. Subject matter categories are then determined to be associated with the content based on the analysis. The mechanism then retrieves profiles for people that are authorized to review and evaluate content. These profiles include identifiers of categories of knowledge that indicate areas of knowledge held by an associated person. A person is then selected based on the subject matter categories and categories of knowledge. The content may then be routed to a client computing device associated with the selected person or group or persons.

Abstract: A method, system and program product for re-meshing of a three-dimensional (3D)input model using progressive implicit approximating levels are provided. Specifically, an initial quadrilateral mesh for a 3D input model is provided. Then, an implicit approximating field is built for a first approximating level (L) of the 3D input model using an implicit surface modeling technique. An iso-contour of the implicit approximating field is then extracted, and the quadrilateral mesh is fit to the first approximating level (L). The fit between the quadrilateral mesh and the first approximating level (L) is then estimated, and it is determined whether the fit meets a predetermined quality criterion. If not, the quadrilateral mesh is refined using one or more of a sequence of topological operations are performed to improve the fit. The process is then iteratively repeated for subsequent approximation levels until one of the subsequent approximation levels is fit to the 3D input model.

Abstract: A structure and method for fabricating a top strap in a magnetic random access memory, MRAM, comprising a damascene process forming a trench in a dielectric layer and resulting in a metal conductor clad on three sides by an inverted U-shape trench liner and cap made up of three layers consisting of a stack of a ferromagnetic material sandwiched between two layers of a refractory metal or an alloy of a refractory metal. First the two sidewalls of the trench are formed with the cladding layer, followed by filling the trench with the metal conductor. In preparing the structure for the capping layer, the metal conductor is recessed with an etch that is selective to the metal conductor over the sidewall stack. This preparation may be performed on selected metal filled trenches and blocked on others, such that after a final polishing step, only those metal conductors that received the recess operation will have the capping layer.

Abstract: The invention provides alkene fluoroalkanol and fluorinated polyol precursors to fluoroalkanol-substituted ?,?-unsaturated esters. The fluoroalkanol-substituted ?,?-unsaturated esters are olefins that can be readily polymerized to provide fluoroalkanol-substituted polymers useful in lithographic photoresist compositions. Also provided are methods for synthesizing the alkene fluoroalkanol and fluorinated polyol precursors.

Abstract: A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.

Abstract: A solution for distributing the workload across the servers (105) in a fail-over cluster (for example, based on the MSCS) is proposed. A fail-over cluster is aimed at providing high availability; for this purpose, a resource service (205) automatically moves each resource (220) that exhibits some sort of failure to another server in the cluster. The proposed solution adds a monitor (240) that periodically measures a responsiveness of each resource. If the responsiveness of a resource is lower than a threshold value, the monitor inquiries a metrics provider (245) for determining the workload of all the servers in the cluster. The monitor then causes the resource service to move that resource to the server having the lowest workload in the cluster.

Abstract: A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series of instructions. Schedule execution of the uniform series of instructions within the loop to optimize execution of the loop in response to the identified series of instructions being the uniform series of instructions.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

Abstract: Name disambiguation by using private/global directories and communication contexts.

Abstract: An IC chip package and related method are disclosed. The IC chip package may include a printed circuit board (PCB) coupled to a chip carrier by a land grid array (LGA) connector; a metal stiffener including at least one force-adjustable member contacting an underside of the PCB; and at least two couplers for coupling the metal stiffener to a lid or a heat sink, with the PCB, the chip carrier and the LGA connector therebetween. The force-adjustable member reduces the required assembly forces and accommodates natural and non-systematic out-of flatness tolerances of the PCB and the chip carrier.

Abstract: A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.

Abstract: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p? substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Abstract: Techniques for providing electrical connections are provided. In one aspect, an electrical connecting device is provided which comprises a plurality of compressible contacts; and a downstop structure surrounding at least a portion of one or more of the contacts, limiting compression of the contacts, and being configured to limit interaction between the contacts. The electrical connecting device may be further configured to have the plurality of compressible contacts have a first coefficient of thermal expansion and the downstop structure have a second coefficient of thermal expansion, the first coefficient of thermal expansion being substantially similar to the second coefficient of thermal expansion.

Abstract: A method and system for determining the memory utilization of a heap are provided. With the method and system, object allocations and optionally, possible memory freeing events are used to initiate a mark-and-count operation. The mark-and-count operation marks the live objects and maintains a running count of their memory bytes allocated to the live objects, referred to as a live count. The execution of the mark-and-count operation may be dependent upon various criteria including thresholds, functions of the live count, peak live counts, number of memory bytes allocated since a previous mark-and-count operation was performed, and the like. In addition to the live count, a total number of bytes allocated to objects may be maintained in order to obtain information regarding the heap memory utilization.

Abstract: Described are a method for generating a session key on demand in a network, a computer program element, a computer program product stored on a computer usable medium, and a computer device for executing the computer program product. The method generates a session key sk on demand in a network among n participating network devices with up to a number t of faulty devices.

Abstract: A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

Abstract: A method, system and article of manufacture for processing rule sets and, more particularly, for processing abstract rule sets. One embodiment provides a computer-implemented method of managing execution of an analysis routine configured to process one or more inputs. The analysis routine is defined by at least one abstract rule set having one or more abstract rules each having a conditional statement and a consequential statement. The method comprises determining, from the retrieved analysis routine, a predefined validating condition that needs to be satisfied by at least one of the inputs, and validating a particular data value defining the at least one of the inputs on the basis of the predefined validating condition. If the particular data value is not validated, a predefined action configured to avoid execution of the analysis routine on invalid inputs is performed.

Abstract: Provided are techniques for transmitting blocks of data. It is determined whether any high priority out of sync (HPOOS) indicator is set to indicate that a number of modified segments associated with a block of data are less than or equal to a modified segments threshold. In response to determining that at least one high priority out of sync indicator is set, one or more sub-blocks of data in the modified segments associated with the block of data and with one set high priority out of sync indicator are transferred.

Abstract: An electrical connector includes a first connector body having an interlocking feature extending therefrom. The interlocking feature interlocks the first connector body with a complimentary interlocking feature extending from an adjacent second connector body to distribute a lateral force on either the first or second connector bodies across the adjacent connector body thereby reducing a rotational moment at a base of each electrical connector connected to a printed circuit board (PCB).