Abstract: Methods, systems, program storage devices and computer program products for mask inspection that automate the detection and placement of do not inspect regions (“DNIR”) for intentionally induced defects on masks. A location of an intentional defect is identified on a mask, and then logic relating to this location is translated into a shape that represents a DNIR for the intentional defect. A second shape representing another DNIR of the mask is provided. It is then determined if the first and second shapes for DNIRs violate a processing rule of the inspection tool, and if so, the violated rule is corrected for by generating a single contiguous DNIR by overlapping the first and second shapes. The inspection tool then utilizes the first and second shapes representing DNIRs, along with any single contiguous DNIRs, to inspect the mask for unintentional defects while avoiding intentional defects.

Abstract: A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.

Abstract: A data storage domain is provided to determine a set of signal conditioning parameters for data being transmitted over smart cables in a data storage domain between an SAS switch and SAS expanders and among SAS expanders. A first expander interrogates any attached smart cables for cable persistent data and captures in a table the cable persistent data. One or more interfaces of the first expander are operated at a first data rate. The switch collects the captured cable persistent data and, in response, determines a set of signal conditioning parameters for data being transmitted on each attached smart cable. The set of signal conditioning parameters includes a first maximum data rate for each attached smart cable. The signal conditioning parameters are then set for each attached smart cable in accordance with the set of determined signal conditioning parameters, whereby the data storage domain is tuned for optimum signal transmission.

Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.

Abstract: The present invention relates to a method for protecting a password. In a first aspect, the method includes allowing a user to enter an apparent password into a computing system, wherein the apparent password is a string of characters and keystrokes including the password and an arbitrary number of non-password related characters and keystrokes. The method further includes analyzing the string of characters and keystrokes by the computing system to find the password, and validating the apparent password if the password is found in any position in the string of characters and keystrokes.

Abstract: Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.

Abstract: A method for recording data freshness degrees by a tape drive is disclosed. During the recording of a set of data and a data freshness degree associated with the set of data a tape recording medium, a determination is made as to whether or not a fault occurs during the recording. In response to a determination that a fault occurs during the recording, a data freshness degree of data within a faulty portion on the tape recording medium is obtained. The data freshness degree of the set of data is then immediately recorded before the faulty portion on the tape recording medium. The data freshness degree is higher than the data freshness degree of data within the faulty portion.

Abstract: An optical control monitor and a method for adjusting for changes in optical signals transmitted through an optical network. The method comprises the steps of transmitting a set of optical signals through a network, each of the optical signals having a respective wavelength; and tracking changes to said set of signals by passing each of the signals through a filter having a bandpass function, and dithering the filter bandpass about the wavelengths of each of said set of signals to generate filter output signals. The filter output signals are used to adjust the network or the set of optical signals to compensate for said changes.

Abstract: The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract: An apparatus for transporting a storage media cartridge in a data storage library is disclosed. The apparatus includes an accessor, a pinion and a rack having a straight section and a curved section. The curved section includes multiple rack teeth that are capable of rotating independently from each other to allow the pinion to travel along the straight section and onto the curved section of the rack, or vice versa, without any interruption.

Abstract: An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in the SOI substrate at a first depth from the substantially planar upper surface, and the second patterned buried insulator layer has a second, different thickness and is located in the SOI substrate at a second, different depth from the substantially planar upper surface. The first and second patterned buried insulator layers are separated from each other by one or more interlayer gaps, which provide body contacts for the SOI substrate. The SOI substrate of the present invention can be readily formed by a method that includes at least two independent ion implantation steps.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: Management of hierarchical identifiers in simulation models and netlists is accomplished using a prefix compressor algorithm running on a general purpose computer processor. Full name compression is accomplished when hierarchy data and remainder data are split off and prefix compressed. Compressing prefixes of names in the hierarchy list is performed by comparing a previous entry to a current entry. Compressing prefixes of names in the name list is performed by running an output of compressing of prefixes of names in the hierarchy list and running an output of the compressing of prefixes of names in the name list through a standard compressor software application package. Decompressing of names uses sub operations inverse to the prefix compressor algorithm. The decompressing sub operations create a string pointed to by the prefix pointer and concatenated onto the string pointed to by the name pointer; and thus a full name is created.

Abstract: Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer by a gate dielectric, dielectric sidewall spacers adjacent to sidewalls of the gate conductor, and source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and implanting metallic species in a bottom region of the semiconductor layer to form a conductive implant region to electrically connect the source junction to the body region.

Abstract: A method, an apparatus, a system, and a computer program product are presented for determining whether a file system, which contains a file system resource that is to be the target of a file system operation, is currently mounted by a data processing system. A first kernel-level process obtains unique identifying information for a file system that contains the target file system resource, and a second kernel-level process manages a data structure having an entry for each file system that the kernel of the data processing system recognizes as being currently mounted. The data structure is searched by the first kernel-level process for an entry having information that matches the unique identifying information such that the first kernel-level process determines that the file system is mounted in response to finding an entry having information that matches the unique identifying information.

Abstract: A computer implemented Availability Checking Tool wherein tool users work within a common work environment, from common enterprise data, and considering assets and demands across multiple order management systems and manufacturing facilities within boundaries established by manufacturing specifications, process flows and business policies. Tool users can easily maintain a synergistic relationship between orders from multiple demand sources or ordering systems. A demand configurator receives demand information from each demand source and coordinates product requests in accordance with customer request rules and priorities. A supply configurator receives manufacturing and planning data from a planning source and manipulates the received manufacturing and planning data to create new supply data. A material resource engine provides material supply information from the new supply data, the received demand information following product supply rules and priorities.

Abstract: Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.

Abstract: An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divider methodology permits the design of advanced circuit functions, such as double data rate memory operations, without the need for additional clock signal sources.

Abstract: Methods and apparatus for authoring and executing an individualized language business rule. In one embodiment, a method comprises creating at least one individualized language resource, creating at least one individualized language rule referencing at least one of said individualized language resource, and transforming said at least one individualized language rule into computer executable format.