Abstract: A system and incorporated method is provided for performing high reliability flash updates using firmware residing in a computing environment. The system comprises a nonvolatile memory having a boot sector and an application sector and a volatile memory in processing communication to update the nonvolatile memory. The volatile memory also includes an implemented algorithm that can temporarily store functions necessary to update the nonvolatile memory via a flash update.

Abstract: The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance.

Abstract: An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link.

Abstract: A solution is proposed for facilitating accessing resources of a data processing system with distributed architecture by a data processing entity of the system (with each resource that is accessible via a corresponding address). A set of bookmarks are provided for corresponding resources. Each bookmark is associated with a stored address of the corresponding resource—for accessing the corresponding resource in response to a selection of the bookmark. In the solution according to an embodiment of the invention, a signature identifying the corresponding resource is associated with each bookmark. Each bookmark is updated by verifying accessibility of the resource at the stored address matches the signature. The resource matching the signature is then located via a search engine in response to the non-accessibility of the resource. It is then possible to replace the stored address with a new address of the located resource.

Abstract: Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.

Abstract: Disclosed is a computer implemented method, apparatus and computer program product for communicating virtual memory page status to a virtual memory manager. An operating system may receive a request to free a virtual memory page from a first application. The operating system determines whether the virtual memory page is free due to an operating system page replacement. Responsive to a determination that the virtual memory page is free due to the operating system page replacement, the operating system inhibits marking the virtual memory page as unused. Finally, the operating system may insert the virtual memory page on an operating system free list.

Abstract: The invention generally relates to semiconductor device processing, and more particularly to methods of accessing semiconductor circuits from the backside using ion-beam and gas-etch to mill deep vias through full-thickness silicon. A method includes creating a pocket in a material to be etched, and performing an isotropic etch of the material by flowing a reactive gas into the pocket and directing a focused ion beam into the pocket.

Abstract: A method includes passing a lot through a production process and evaluating a statistical quality of the production process. Additionally, the method includes calculating an advanced process control (APC) recipe parameter adjustment (RPA) distribution value and determining if sampling is indicated. Furthermore, the method includes, if sampling is indicated, performing a measurement process of the lot.

Abstract: Systems and methods for cooling electronic devices via enhanced thermal conduction in the gap separating an electronic device from a heat sink are provided. In one embodiment, a system for cooling an electronic device comprises: a heat sink spaced from the integrated circuit by a gap; and a bubbler and an atomizer configured to feed a mixture comprising an atomized liquid and a carrier gas to the gap.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract: A mask having a plurality of through holes and a mold having a plurality of cavities are provided, and the through holes and the cavities are aligned. Conductive balls are dispensed into the aligned through holes and cavities. Substantially one ball is dispensed into each aligned through hole and cavity, and the mask with the holes and the cavities in the mold are configured and dimensioned such that the balls are substantially flush with, or recessed below, an outer surface of the mask. The mask is removed, the conductive balls are aligned with pads of a semiconductor device, and the conductive balls are transferred to the pads by fluxless reflow in a formic acid environment. Vibrational, electrostatic, and direct transfer aspects are also disclosed.

Abstract: Computer-implemented methods, apparatus, and products for administering IM chat sessions including: identifying, by an IM module in dependence upon a merger policy, a plurality of IM participants to merge into a group IM chat session, the IM module providing IM services to one of the participants; and merging, by the IM module, the identified participants into the group IM chat session.

Abstract: A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The message comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and then a partial least squares regression is performed on the joined data set to obtain a prediction equation, and a variable importance prediction for each process window in a process window set. A set of product limited yield are derived, and the process window set is adjusted, and the yields recalculated, until an optimal process window set is derived.

Abstract: A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value.

Abstract: A method and a system for relating of a value network analysis of a mission to a knowledge base of dependencies of data objects, applications and information technology resources required for achieving of such mission, such method used for optimization of provisioning for information technology resources and for prioritizing of control of data and application security and integrity of such mission.

Abstract: In some embodiments, a method for determining meeting participants in an electronic calendar comprises identifying, based on user input, a first set of participants to invite to a meeting scheduled in the electronic calendar, wherein the meeting is associated with a topic. The method can also comprise identifying a second set of participants based on the topic associated with the meeting. The method can include determining a union of the first and second sets of participants and generating, for this union, calendar entries in the electronic calendar. The method can also include presenting the calendar entries in the electronic calendar.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A method, system and computer program product for performing pattern matching in parallel for a plurality of input streams. The method includes calculating a memory address in a translation table responsive to a current input value, a current state and current state information. A transition rule is retrieved from the transition rule table at the memory address, the transition rule including a test input value, a test current state, and next state information. It is determined if the current input value and the current state match the test input value and the test current state. The current state information is updated with the next state information in response to determining that the current input value and the current state match the test input value and the test current state. The current state information is updated with contents of a default transition rule in response to determining that the current input value and the current state do not match the test input value and the test current state.

Abstract: A computer implemented method, apparatus, and program product for extending virtual memory associated with logical partitions. A hosting partition receives a paging request from a logical partition on a logically partitioned data processing. The hosting partition identifies a location of the physical memory space on a remote computing device assigned to the logical partition and sends an extended virtual memory paging request to an extended virtual memory manager located on the remote computing device using a network connection. The extended virtual memory paging request comprises the instructions for the memory page-in or the memory page-out and the location of the physical memory space on the remote computing device that is being paged-in or paged-out. The extended virtual memory manager performs a page-in operation or a page-out operation in accordance with the instructions for the memory page-in or memory page-out.