Abstract: Hypervisor managed memory paging is provided in a data processing system having multiple logical partitions. The data processing system includes a shared memory pool defined within physical memory. The shared memory pool includes a volume of physical memory with dynamically adjustable sub-volumes or sets of physical pages associated with the multiple logical partitions. Each sub-volume or set is associated with a particular logical partition and includes mapped logical memory pages for that logical partition. A hypervisor memory manager interfaces the multiple logical partitions and the shared memory pool, and manages access to logical memory pages within the shared memory pool. The hypervisor memory manager further manages page-out and page-in of logical memory pages from the shared memory pool to one or more external paging devices. This page-out and page-in managing by the hypervisor memory manager is transparent to the multiple logical partitions.

Abstract: The invention generally relates to ventilation systems and methods, and more particularly to selectively configurable climate control systems and methods for use in data centers and the like. A method includes receiving or obtaining input data, generating at least one actuation signal to change a flow configuration of a re-configurable duct system based upon the input data, and transmitting the at least one actuation signal.

Abstract: The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

Abstract: A statistical tree representing an extensible Markup Language (XML) Schema document (XSD) is generated. The statistical tree captures information defined by the XSD by representing elements, attributes, and enumerations of the XSD as branches, nodes, and leaves of the statistical tree. The statistical tree has bits corresponding to nodes of the statistical tree. An XML document defined by the XSD is adaptively encoded, or compressed, as a number of bits based on the statistical tree that has been generated. The number of bits encoding the XML document are decoded, or decompressed, to yield the XML document also based on the statistical tree that has been generated.

Abstract: Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.

Abstract: Autonomic correction of incorrect identities in repositories. A communication is prepared and sent to one or more recipients. In response thereto, a notification is provided to the sender that one or more of the recipient's identities is incorrect. Based on this notification, corrective action is automatically initiated in order to locate the repository, and in particular, an entry in the repository corresponding to the incorrect identity and to take action to correct that identity.

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Abstract: A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: A system and associated method for mutually exclusively executing a critical section by a process in a computer system. The critical section accessing a shared resource is controlled by a lock. The method measures a detection time when a lock contention is detected, a wait time representing a duration of wait for the lock at each failed attempt to acquire the lock, and a delay representing a total lapse of time from the detection time till the lock is acquired. The delay is logged and used to calculate an average delay, which is compared with a suspension overhead time of the computer system on which the method is executed to determine whether to spin or to suspend the process while waiting for the lock to be released.

Abstract: The present invention provides a method for selectively placing carbon nanotubes on a substrate surface by using functionalized carbon nanotubes having an organic compound that is covalently bonded to such carbon nanotubes. The organic compound comprises at least two functional groups, the first of which is capable of forming covalent bonds with carbon nanotubes, and the second of which is capable of selectively bonding metal oxides. Such functionalized carbon nanotubes are contacted with a substrate surface that has at least one portion containing a metal oxide. The second functional group of the organic compound selectively bonds to the metal oxide, so as to selectively place the functionalized carbon nanotubes on the at least one portion of the substrate surface that comprises the metal oxide.

Abstract: A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation information, instruction sequences, base register available, target real memory pages, etc. In turn, the micro generator tests a processor using the initial test cases and subsequent test cases generated by the micro generator. The subsequent test cases may include modified test case properties such as changed machine state register bits, changed instruction sequence (shuffling), changed effective segment ID bits, and/or changed virtual segment ID bits. In addition to generating subsequent test cases, the micro generator performs functions such as test case dispatching, test case scheduling, test case execution, and interrupt handling.

Abstract: Mapping computers and ports of power distribution units in a data center, the data center including a plurality of computers and a data center management server, each computer in the data center connected for power to one of a plurality of power distribution unit (‘PDU’) ports of a PDU, each PDU connected through the communications module and a data communications network to the data center management server, including generating, by a power modulating module of a computer, a power consumption signal in the PDU, the power consumption signal encoding a unique identification of the computer; demodulating, by the PDU, the power consumption signal, including retrieving from the signal the unique identification of the computer; and reporting, by the PDU to the data center management server, an association of the unique identification of the computer and a PDU port.

Abstract: Automated paging device management is provided for a shared memory partition data processing system. The automated approach includes managing a paging storage pool defined within one or more storage devices for holding logical memory pages external to physical memory managed by a hypervisor of the processing system. The managing includes: responsive to creation of a logical partition within the processing system, automatically defining a logical volume in the paging storage pool for use as a paging device for the new logical partition, the automatically defining occurring absent use of a filesystem, with the resultant paging device being other than a file in a filesystem; and automatically specifying the logical volume as a paging space device for the new logical partition and binding the paging space device to the new logical partition, wherein the logical volume is sized to accommodate a defined maximum memory size of the new logical partition.

Abstract: Disclosed is a computer implemented method and apparatus for marking as critical a virtual memory page in a data processing system. An operating system indicates to a virtual memory manager a virtual memory page selected for paging-out to disk. The operating system determines that the data processing system is using a cooperative memory over-commitment. The operating system, responsive to a determination that the data processing system is using cooperative memory over-commitment, marks the virtual memory page as critical, such that the virtual memory page remains in physical memory. The operating system, responsive to marking the virtual memory page as critical, sets the virtual memory page to a page-out state.

Abstract: An automated disaster recovery (DR) planning system for a computing environment is provided. A discovery module discovers servers, networks, and storage devices in a computing environment. An expert knowledge base module captures best practices in planning, and capabilities, interoperability, limitation and boundary values for different DR technologies. A match-making module determines multiple DR plans as combinations of one or more replication technologies that can be used to satisfy DR requirements. And, an optimizer configured for assessing a feasible DR plan from said multiple DR plans, to deploy for DR planning of a primary computing environment.

Abstract: Methods, apparatus, and products are disclosed for budget-based power consumption for application execution on a plurality of compute nodes that include: assigning an execution priority to each of one or more applications; executing, on the plurality of compute nodes, the applications according to the execution priorities assigned to the applications at an initial power level provided to the compute nodes until a predetermined power consumption threshold is reached; and applying, upon reaching the predetermined power consumption threshold, one or more power conservation actions to reduce power consumption of the plurality of compute nodes during execution of the applications.

Abstract: The present invention discloses a data tag device (100) which initially operates in an active mode where the tag occasionally transmits an unsolicited beacon (412). While operating, an expiration event occurs (512, 514) which causes the tag to disable a battery (110), preventing subsequent operation in an active mode, but may continue operating in a passive mode.

Abstract: In one embodiment, a computer implemented method for indexing security policies is provided. The computer implemented method determines a policy vocabulary to form a set of policy elements, and creates an index from the set of policy elements. The computer implemented method further receives a request to form requested policy elements, locates requested policy elements in the index to form a set of returned policy elements, and identifies a rule for use with the returned policy elements.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.