Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A high voltage MOSgated semiconductor device has a generally linear MOSFET type forward current versus forward voltage characteristic at low voltage and the high current, low forward drop capability of an IGBT. The device is particularly useful as the control transistor for a television tube deflection coil. The device is formed by a copacked discrete IGBT die and power MOSFET die in which the ratio of the MOSFET die area is preferably about 25% that of the IGBT. Alternatively, the IGBT and MOSFET can be integrated into the same die, with the IGBT and MOSFET elements alternating laterally with one another and overlying respective P+ injection regions and N+ contact regions respectively on the bottom of the die. The MOSFET and IGBT elements are preferably spaced apart by a distance of about 1 minority carrier length (50-100 microns for a 1500 volt device).

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract: A novel five-layer tape is provided for applications such as bonding, interconnection and insulation of different parts of a semiconductor package at the same time. The five layer tape includes a metal conductive layer that is sandwiched between two insulative layers, that are themselves in turn sandwiched by two adhesive layers. Windows cut into the insulative and adhesive layers on either the top or bottom of the tape permit electrical connection to the metallic conductive layer. The tape may be made from two insulation sheets that have an adhesive layer and a metallic interconnect. In turn, the tape enables the manufacturer to overcome physical limitations in forming conduction paths, including permitting the connection of multiple die where the terminals of the one die are obscured by the other die.

Abstract: A termination structure for a superjunction device on which the net charge between P pylons in an N− termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.

Abstract: An integrated circuit with both ballast control and driver circuitry and power factor correction (PFC) control circuitry. At the beginning of preheating, power is provided to the load circuit at a voltage below a voltage at which the lamp can ignite, and the PFC control circuitry can then bring the DC bus voltage up to its running value. For this purpose, the PFC circuitry is enabled depending on the mode of the ballast control and driver circuitry. The DC bus voltage is regulated at a lower loop speed when the lamp is running than when the lamp is ramping to ignition, to alleviate DC bus droop. A criterion is applied to determine whether over-current detect signals indicate an actual fault. For this purpose, detect signals during ignition ramping can be counted and compared with a fault number. A lamp end-of-life condition can be detected by comparing sensed voltage with upper and lower window voltages. When a lamp is off for only a short time, it can be quickly restarted without full preheating.

Abstract: A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with a single common layer of conductive polysilicon which extends into each trench and overlies the silicon surface which connects adjacent trenches. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The trench is from 0.2 to 0.25 microns deeper than the channel region. The device has a very low figure of merit and is useful especially in low voltage circuits.

Abstract: A circuit for suppressing false operation of a level shift circuit due to a noise transient, the circuit comprising a first transistor coupled to a voltage source of the level shift circuit and being coupled to pass a current when a noise transient is present on the voltage source an output terminal coupled to the first transistor providing as an injected signal a current proportional to the current in the first transistor to at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

Abstract: A switching converter comprising: a first switch having a first terminal adapted to be coupled to a first DC voltage, an inductor having a first terminal coupled to a second terminal of the first switch; the inductor having a tap and a second terminal; the second terminal coupled to a capacitor, the capacitor adapted to have a second DC voltage thereon; and a second switch having a first terminal coupled to the tap of the inductor and a second terminal coupled to a common line coupling said first and second DC voltages.

Abstract: A high voltage vertical conduction semiconductor device has a plurality of deep trenches or holes in a lightly doped body of one conductivity type. A diffusion of the other conductivity type is formed in the trench walls to a depth and a concentration which matches that of the body so that, under reverse blocking, both regions fully deplete. The elongated trench or hole is filled with a dielectric which may be a composite of nitride and oxide layers having a lateral dimension change matched to that of the silicon. The filler may also be a highly resistive SIPOS which permits leakage current flow from source to drain to ensure a uniform electric field distribution along the length of the trench during blocking.

Abstract: A superjunction device has a plurality of equally spaced P columns in an N− epitaxial layer. The concentration of the P type columns is made greater than that needed for maintaining charge balance in the N− epi region and the P columns thereby to increase avalanche energy. An implant dose of 1.1E13 or greater is used to form the P columns.

Abstract: A polysilicon FET is built atop a SiC diode to form a MOSgated device. The polysilicon FET includes an invertible layer of polysilicon atop the surface of a SiC diode which has spaced diode diffusions. A MOSgate is formed on the polysilicon layer and the energization of the gate causes an inversion channel in the invertible layer to form a majority carrier conduction path from a top source electrode to a bottom drain electrode. Forward voltage is blocked in part by the polysilicon FET and in larger part by the depletion of the silicon carbide area between the spaced diode diffusions.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: A fluorescent lamp ballast circuit including a phase cut dimmer connectable to a source of AC power, the selectable phase cut dimmer and an electronic switch having a trigger voltage and a conduction period, when the electronic switch triggers to the end of the half cycle, a rectifying and charging circuit coupled to the output of the phase cut dimmer for providing a DC voltage across a DC bus, a filter circuit receiving the output of said phase cut dimmer and converting the output to a control signal related to the firing angle of the electronic switch; an output stage coupled to the lamp, the output stage having at least one electronic switching device; the ballast control circuit including a control input for changing a frequency of said pulsed power signal, the control input being coupled to said control signal, the control signal varying in accordance with the firing angle of he electronic switch, thereby varying the brightness level of said fluorescent lamp.

Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. An annular flange may also be embedded in the plastic molded insulation ring and connected to an annular rib of a pole piece by a circular connector.

Abstract: A high voltage integrated circuit (HVIC) chip with a resistor connected between the substrate of the chip and ground. The resistor substantially improves the handling of negative voltage spikes by limiting the current passing through the intrinsic diode of the chip when the diode conducts due to negative transients at the output node.

Abstract: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected.

Abstract: A driver stage consisting of an N channel FET and a P channel FET are mounted in the same package as the main power FET. The power FET is mounted on a lead frame and the driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame terminals. All electrodes are interconnected within the package by mounting on common conductive surfaces or by wire bonding. The drivers are connected to define either an inverting or non-inverting drive.

Abstract: Motor insulation degradation is determined using circuitry to sense the common mode leakage current from the ground wire cable. In a preferred embodiment of the invention, a small current transformer detects the common mode leakage current flowing in the ground wire cable of the motor controller circuit. A single pole low pass filter generates an average leakage current signal from the sensed current. The average leakage current signal is converted to a PWM signal. A pulse generator receives the PWM signal and generates pulse signals at the rising and falling edges of the PWM signal. A pair of level shifters receive the rising edge and falling edge pulse signals and transpose those signals from a floating high voltage to a voltage referenced to ground. A pulse reconstruction circuit receives the level shifted pulse signals and reconstructs a pulse width modulated signal having a duty cycle which varies with respect to the magnitude of the common mode leakage current.