Abstract: A digital level shift circuit includes a level shifting device such as a high voltage MOS device and can also include feedback circuitry. The level shifting device is turned on to make an output transition, and the feedback circuitry obtains a feedback or acknowledge signal indicating that the transition was made. In response, the feedback circuitry turns off the level shifting device, which can reduce power dissipation. A digital level shift circuit that includes two n-channel devices and two p-channel devices can also include sense/prevent circuitry that senses when current greater than a threshold flows through both devices of one channel type and, in response, prevents output transitions from being made, which can avoid false transmissions due to rapid changes in offset voltage. Control circuitry in a digital level shift circuit can include both feedback circuitry and sense-prevent circuitry.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.

Abstract: An inductive load driven by power MOSFETs, such as in a low voltage motor drive, using synchronous rectification to reduce the voltage drop across a body diode of a power MOSFET. A comparative feed back circuit measures voltage across the power MOSFET to determine when the body diode is conducting, and turns the MOSFET ON during conductive cycles, and OFF to block reverse current. The obtained synchronous rectification function is highly sensitive to current flow, while using a very small number of parts in a configuration that has less complexity.

Abstract: A computer program for calculating temperature rise profiles of a power MOSFET for different current waveforms, either single waveforms or multiple waveforms. The user enters the device part number identifying the device, the device Rdson at maximum temperature, and various calculation data, such as the calculation resolution and thermal resistance coordinates. The user also selects the desired current waveform from a library of waveforms. The program then calculates thermal resistance constants for the device as a function of time, and generates an array of thermal resistance values for each waveform subdivision based on the calculation resolution chosen. The instantaneous power values at each current/time subdivision are then calculated by the program and an array of power×thermal resistance difference terms is generated for each time interval. These terms are then summed to generate the temperature rise profile, and the results are displayed graphically or textually.

Abstract: A power control circuit includes sensing circuitry for sensing information about operation of a power device such as an IGBT or other power FET. The sensing circuitry receives a sense input signal from the power device through a gating device such as a diode. The power control circuit also includes active impedance circuitry for preventing the sense input signal from including spurious information received from the gating device. For example, if the gating device is a diode across which negative spikes can be capacitively coupled, the active impedance circuitry can prevent the negative spikes from reaching the sensing circuitry when the diode is off. The active impedance circuitry can take the form of a transistor connected between a power supply and a sensing node. The active impedance device can be switched on by a comparator when the voltage across the power device exceeds a reference voltage, indicating the power device is off.

Abstract: A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.

Abstract: Semiconductor devices having recombination centers comprised of well-positioned heavy metals. At least one lattice defect region within the semiconductor device is first created using particle beam implantation. Use of particle beam implantation positions the lattice defect region(s) with high accuracy in the semiconductor device. A heavy metal implantation treatment of the device is applied. The lattice defects created by the particle beam implantation act as gettering sites for the heavy metal implantation. Thus, after the creation of lattice defects and heavy metal diffusion, the heavy metal atoms are concentrated in the well-positioned lattice defect region(s).

Abstract: A magnetic field measuring device useful for measuring a magnetic field associated with an electric current, including a bus section connectable into the path of the electric current, a first magnetoresistive (MR) bridge oriented to be sensitive to the magnetic field of a current in the bus section, a second MR bridge oriented to be substantially insensitive to the magnetic field of a current in the bus section, a biasing coil configured and positioned to apply a magnetic field to the first and second MR bridges, whereby the sensitivity of the first MR bridge can be controlled; and a signal processing device responsive to a voltage output of the second MR bridge to control the current through the biasing coil. The device exhibits good rejection of stray magnetic and electric fields, is convenient to use, and can be fabricated in a single chip, with or without associated signal processing and conditioning circuitry, using conventional IC processing techniques.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: A ballast controller integrated circuit which executes a specific set of instructions via an integrated state diagram architecture to control a fluorescent lamp or high intensity discharge lamp and protect the ballast. The state diagram architecture controls powering up and down of the IC and the half-bridge circuit driven by the IC, preheating and striking of the lamp, running of the lamp, sensing for numerous possible fault conditions, and recovering from these fault conditions based on the normal maintenance of a lamp, while requiring fewer internal and external components than previous electronic ballasts.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings in an implant and drive system. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or palladium contact layer. A thin high resistivity layer of amorphous silicon is deposited over the full upper surface of the wafer and is disposed between the wafer upper surface and all of the metal rings.

Abstract: The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

Abstract: Circuits for communicating between high side devices and low side controllers without using level shifting switches are provided. A low voltage controller with time coding circuitry generates an output, such as a voltage, a current, or a digital signal for controlling a high side switch. A driver is connected to the high side switch and receives the signal from the controller, decodes the signal, and generates on and off time pulses for controlling the high side switch. The communication between the controller and the driver does not require any level shifting circuitry.

Abstract: A P channel high voltage metal oxide semiconductor device is described which is integrated in the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices. The high voltage device has a lightly doped p− drift region adjacent to the heavily doped p+ drain region. A high voltage support region is formed directly below the drift region using high energy ion implantation with an implantation energy of between about 2 and 3 Mev. This high energy ion implantation is used to precisely locate the high voltage support region directly below the drift region. This high voltage support region avoids punch-through from the P channel drain through the drift region into the substrate while using a standard depth for the n type well. This allows the high voltage device to be integrated into the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices.

Abstract: A superjunction device has a plurality of equally spaced P columns in an N− epitaxial layer. The concentration of the P type columns is made greater than that needed for maintaining charge balance in the N− epi region and the P columns thereby to increase avalanche energy. An implant dose of 1.1E13 or greater is used to form the P columns.

Abstract: A contact clip for the aluminum contact of a semiconductor device has a central nickel-iron body, preferably Nilo alloy 42, which is coated on top and bottom by a soft, but high conductivity metal such as gold, silver or copper. The nickel-iron body has a thickness of about 15 mils, and is about the thickness of the silicon die. The conductive layers have a thickness of about 5% to 20% of that of the nickel-iron core.

Abstract: A superjunction device has a large number of symmetrically located vertical circular wells in a high resistivity silicon substrate. A plurality of alternate opposite conductivity N and P stripes or nodes are formed along the length of the walls of each of the wells. Each of the nodes faces an opposite concentration type node in an adjacent well. A DMOS gate structure is connected to the tops of the N stripes. The nodes have a depth and concentration to cause full depletion of all nodes during reverse bias. Current flows through the relatively low resistance N stripes when its gate is turned on. A conventional termination such as a diffused ring or rings can surround the active area of all cells and is formed in the high resistivity substrate.

Abstract: A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.

Abstract: A process is described for making a superjunction semiconductor device, a large number of symmetrically spaced trenches penetrate the N− epitaxial layer of silicon atop an N+ body to a depth of 35 to 40 microns. The wells have a circular cross-section and a diameter of about 9 microns. The trench walls are implanted by an ion implant beam of boron which is at a slight angle to the axis of the trenches. The wafer is intermittently or continuously rotated about an axis less than 90° to its surface to cause skewing of the implant beam and more uniform distribution of boron ions over the interior surfaces of the trenches.

Abstract: A lead frame for a high power semiconductor device die has three external lead conductors, the outer two of which are reentrantly bent outwardly from the center of the lead frame. When the lead frame is overmolded, the outer conductors are spaced from a central conductor by an increased creepage distance along the plastic surface of the housing. Further, the lead sequence of the exterior leads is gate, source, drain for a power MOSFET. The post area for wire bonding to the source post is enlarged to permit wire bonding with at least three bond wires. The external conductors can be downwardly bent to form a surface mount device. The cross-sectional area of the external conductors is substantially enlarged, although only a small enlargement of the circuit board hole is needed. The package outline has a long flat area centered over the main die area, with a tapered end surface which allows the package to pry open a mounting spring for surface mounting of the package.