Abstract: A multiphase DC-to-DC converter includes at least two phase circuits each having upper and lower power switches and a front-end inductor that is operative for forming a resonant tank circuit with the phase circuits to ensure zero voltage switching and minimizing power losses.

Abstract: A tracking soft start circuit architecture contains a plurality of soft start circuits for generating a plurality of soft start voltages during startup for application to associated power supply terminals of a power supply system. The soft start circuits are interconnected in such a manner that prevents any soft start circuit from generating a soft start voltage waveform until all of the controlled power output devices have been brought to the same prescribed state of operation, that is, all power FET gates are precharged and their source voltages match each other.

Abstract: A voltage regulator exhibits a load line that is piecewise linear. This piecewise linearity variation has a first constant voltage segment VLEAK at which output voltage is regulated for output currents less than or equal to the leakage current IL. The output voltage VLEAK corresponds to the maximum output voltage allowable at the leakage current for a given operational range specification. The piecewise linearity variation further includes a second, linearly decreasing segment that varies from the maximum allowable output voltage VLEAK at the leakage current to a full load voltage VDROOP at full load current IFL. This serves to effectively maximize the available output voltage swing in the presence of a leakage current offset. The piecewise linear load line is adjustable to accommodate changes in leakage current.

Abstract: A soft start circuit for a DC-DC converter has an input reference voltage coupled to an error amplifier and to a soft start capacitor. A feedback resistor is coupled between an output node and the error amplifier, whose output is coupled to a pulse width modulator (PWM). The PWM output is coupled through an inductor to the output node, to which an output capacitor referenced to ground is coupled. Means is provided to charge up the soft start capacitor to the output voltage while the converter is disabled. As a result, when enabled, the converter will not discharge the output capacitor, but will ramp the output voltage to the voltage Vref without excessive currents.

Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

Abstract: A multi-phase DC-DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.