Abstract: A photodetector includes one or more first photodiode regions that are covered by an optical filter configured to reject infrared (IR) light and that produce a first current (I1). The photodetector also includes one or more second photodiode regions that are covered by a light blocking material configured to reject visible and infrared light and that produce a second current (I2). The photodetector also includes one or more third photodiode regions that are not covered by the optical filter and are not covered by the light blocking material and that produce a third current (I3). Additionally, the photodetector includes circuitry configured to produce an output indicative of the first current (I1) or a scaled version of the first current (I1), minus the second current (I2) or a scaled version of the second current (I2), minus the third current (I3) or a scaled version of the third current (I3). The optical filter configured to reject IR light can be, e.g.

Abstract: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.

Abstract: An embodiment of a controller for a power supply includes circuitry that is operable to allow the power supply to operate as follows. During a first portion of a supply period, a first current flows through a first winding of the power supply, through a second winding of the power supply, and to an output node of the power supply. And during a second portion of the supply period, a second current flows through the first winding, through a third winding of the power supply, and to the output node. Each of the first, second, and third windings may be non-electrically isolated from one or more of the other windings during one or more portions of the supply period. Furthermore, the first, second, and third windings may be magnetically coupled to one another. For example, in an embodiment, such a controller may be part of a DC-DC converter that may be more efficient, and that may have reduced interdependence between output-signal ripple and transient response, than a conventional buck converter.

Abstract: A system, voltage supply circuit, control unit for a voltage supply circuit, and method of controlling a voltage supply circuit are disclosed. For example, a system is disclosed that comprises at least one electronic circuit and a voltage supply unit coupled to an input of the at least one electronic circuit. The voltage supply unit includes a power unit to supply a voltage to the at least one electronic circuit and a control unit to control an operating mode of the power unit, an output of the control unit coupled to an input of the power unit. The control unit includes a mode selector to select the operating mode of the power unit, coupled to at least a first output of the power unit, an amplifier coupled to the at least a first output of the power unit, a compensation circuit, and a first switching unit coupled to the mode selector and the compensation circuit, to couple the compensation circuit to the amplifier if a selected operating mode of the power unit is a first mode.

Abstract: A method for operating a voltage regulator controller, for use in a voltage regulator including coupled inductors, is provided as follows. A first signal is generated for driving a first switch of the voltage regulator. A second signal is generated driving a first switch of the voltage regulator. The voltage regulator determines whether a light-load condition exists. Upon determining the existence of a light-load condition, adjusting the phase difference between said first and second signals so that the first and second signals are approximately in-phase.

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk?Xmean. The sign of each offset error, i.e., sign (Xk?Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC.

Abstract: An apparatus and method for controlling the operation of a utility device, such as a cold cathode fluorescent lamp that is powered in accordance with a pulse width modulation (PWM) signal, includes an analog sensor which monitors the utility device to derive an output signal representative of the PWM signal. An integrating analog-to-digital converter (ADC), which is coupled to the sensor and has its operation synchronized with an integral multiple of the period of the PWM signal, produces an output representative of an average of the output of the utility device.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.

Abstract: A method of providing threshold voltage monitoring and control in synchronous power converters is disclosed. The method establishes a threshold voltage level for at least one of an upper gate and a lower gate power switch in a synchronous power converter. The threshold voltage levels indicate switching delay times are present in the upper and lower gate power switches. The method detects body diode conduction levels for both the upper and lower gate power switches. When at least one of the detected body diode conduction levels exceed a prescribed body diode conduction level, the method adjusts the threshold voltage level for at least one of the upper and lower gate power switches to reduce a body diode conduction time for the at least one of the upper and lower gate power switches.

Abstract: In an embodiment, a proximity sensor includes a driver, a photo-diode (PD) and an analog-to-digital converter (ADC). The proximity sensor can also include a controller to control the driver. The driver selectively drives a light source, e.g., an infrared (IR) light emitting diode (LED). The PD, which produces a current signal indicative of the intensity of light detected by the PD, is capable of detecting both ambient light and light produced by the light source that is reflected off an object. The ADC receives one or more portion of the current signal produced by the PD. The ADC produces one or more digital output that can be used to estimate the proximity of an object to the PD in a manner that compensates for ambient light detected by the PD and transient changes to the detected ambient light.

Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.

Abstract: A battery charger comprises charging circuitry for providing a battery charging voltage responsive to an input voltage. First circuitry provides both over-voltage protection and an input voltage bypass signal responsive to the input voltage. The first circuitry includes a low impedance switch having a resistance of at least 500 m? for connecting the input voltage to an output voltage node. The first circuit also includes a higher impedance switch having a resistance of at least 1000 m? for providing the input voltage as a voltage bypass signal.

Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.

Abstract: A phase doubler driver circuit includes first control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to an input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal.

Abstract: A method for operating a voltage regulator controller, for use in a voltage regulator including coupled inductors, is provided as follows. A first signal is generated for driving a first switch of the voltage regulator. A second signal is generated driving a first switch of the voltage regulator. The voltage regulator determines whether a light-load condition exists. Upon determining the existence of a light-load condition, adjusting the phase difference between said first and second signals so that the first and second signals are approximately in-phase.

Abstract: A circuit for improved sampler linearity, in an analog to digital converter, by taking simultaneous analog samples of an input signal V(t) and its derivative, dV/dt. The correction can be implemented as a memoryless non-linear model in the analog, digital, or mixed signal domains. Delay elements placed in the clock signal path or main input signal path can provide more precise control over the correction.

Abstract: An instrumentation amplifier includes a pair of buffered operational amplifiers that accept a pair of input signals, and a differential operational amplifier that outputs an output signal indicative of a difference between the input signals. A low pass filter provides passive band limiting of the output signal. Each operational amplifier is implemented as a multi-path amplifier that includes a low frequency path and a high frequency path between an input and an output of the operational amplifier. Further, each multi-path amplifier includes a differential input transconductance stage within the low frequency path and a differential input transconductance stage within the high frequency path. Within each multi-path amplifier, the differential input transconductance stage of the high frequency path is noisier than, but consumes less power than, the differential input transconductance stage of the low frequency path.

Abstract: A circuit in accordance with an embodiment of the present invention includes an instrumentation amplifier, a dynamically adjustable low pass filter, at least one monitor and a controller. The instrumentation amplifier includes a pair of buffered operational amplifiers that accept a pair of input signals, and a differential operational amplifier that outputs an output signal indicative of a difference between the pair of input signals. The dynamically adjustable low pass filter is configured to provide band limiting of the output signal at frequencies greater than a cutoff frequency. The monitor, or monitors, is/are configured to monitor a signal upstream of the instrumentation amplifier and/or a signal downstream of the instrumentation amplifier and output a monitor signal.

Abstract: A system comprising a first serializer/deserializer coupled to a first electronic device and a second serializer/deserializer couple to a second electronic device is provided. The first serializer/deserializer comprises a forward channel driver and the second serializer/deserializer comprises a reverse channel driver. A communication medium is coupled between the first and second serializer/deserializers, and the first and second serializer/deserializers are AC coupled to the communication medium to provide a high frequency forward channel and are DC coupled to the communication medium to provide a low frequency reverse channel.

Abstract: A voltage regulator circuit arrangement limits the DC voltage applied to a tip and ring amplifiers of a subscriber line interface circuit (SLIC), each of which has a first polarity input coupled to a first current flow path to which a DC input (battery) voltage is coupled. A first current source supplies a first current derived via a low pass filter path from that flowing through the first current flow path to a second polarity input node of the tip amplifier, while a second current source supplies a similarly low pass filter path-derived second current to a second polarity input node of the ring amplifier. A voltage regulator is coupled with the first current flow path and is operative to regulate the voltage at the first polarity inputs of the tip and ring amplifiers to a regulated voltage value Vreg, so that the magnitudes of the first and second currents are based upon the regulated voltage value Vreg.