Abstract: An embodiment of a power-supply controller includes first and second circuits. The first circuit is operable to cause a first current to flow through a first phase of a power supply. And the second circuit is operable to cause the second phase of the power supply to operate in a reduced-power-dissipation mode for at least a portion of a time period during which a second current magnetically induced by the first current flows through the second phase.

Abstract: A voltage error signal VERR is provided to a PWM controller of a voltage regular and used to produce a PWM signal that drives a power stage of the regulator. When operating in an adaptor current limit regulation mode, an adaptor current sense voltage VACS, indicative of an adapter current IA, is compared to an adapter current reference voltage VAC_REF to produce an adapter current error signal VAC_ERR. A compensator receives the adapter current error signal VAC_ERR and outputs a compensated adapter current error signal. The adaptor current sense voltage VACS, or a high pass filtered version thereof, is subtracted from the compensated adapter current error signal to produce the voltage error signal VERR provided to the PWM controller. Alternatively, an input voltage VIN, or a high pass filtered version thereof, is added to the compensated adapter current error signal to produce the voltage error signal VERR.

Abstract: A system, power supplies, controller and method for enhanced phase current sharing are disclosed. For example, a power supply for enhanced phase current sharing is disclosed, which includes a plurality of power modules, a communication bus coupled to an input of each power module of the plurality power modules, and an output voltage node coupled to a first side of an inductor of each power module of the plurality of power modules, wherein each power module of the plurality of power modules includes a digital controller coupled to the input of the power module, and an RC circuit enabled to generate a feedback signal, coupled to a second side of the inductor and the output voltage node. In some implementations, the power supply is at least part of a power management integrated circuit (PMIC) or at least part of a power supply formed on a semiconductor IC, wafer, chip or die.

Abstract: In an embodiment, a power-supply controller includes a switching regulator and a current limiter. The switching regulator is configured to generate an input current such that an output voltage is generated in response to the input current and an input voltage, and the current limiter is configured to limit the input current in response to a quantity that is related to a ratio of the output voltage divided by the input voltage. For example, an embodiment of such a power-supply controller may be able to limit the output or load current from a power supply to a set level by limiting the input current in response to a quantity that is related to the ratio (e.g., the boost ratio) of the output voltage to the input voltage.

Abstract: The system and method creates a substantially constant output voltage ripple in a buck converter in discontinuous conduction mode by varying the on-time of a pulse width modulator (PWM) signal driving the buck converter when the buck converter is operating in discontinuous conduction mode. A first signal is generated that is a function of the switching frequency of the buck converter. This signal is low-pass filtered and compared with a second signal that is a function of the switching frequency of the buck converter when operating in continuous conduction mode and with constant PWM on-time. The output signal generated by the comparator is a signal that is equal to the ratio of the first signal and the second signal. The on-time of a voltage controlled oscillator is controlled by the output signal, the oscillator signal causing the on-time of the PWM signal to vary in a controlled fashion.

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract: A method for wafer level fabricating a plurality of optoelectronic devices, starting with a wafer that includes a plurality of light detector sensor regions, includes attaching each of a plurality of light source dies to one of a plurality of bond pads on a top surface of the wafer that includes the plurality of light detector sensor regions. The method also includes attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, wherein the preformed opaque structure includes opaque vertical optical barriers. Additionally, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is diced to separate the wafer into a plurality of optoelectronic devices, each of which includes at least one of the light detector sensor regions, at least one of the light source dies and at least two of the solder balls or other electrical connectors.

Abstract: In an embodiment, an apparatus, such as a power-supply controller, includes a generator and an adjuster. The generator is configured to provide a switching signal that causes a power supply to generate a regulated output signal, and the adjuster is configured to impart a condition to the power supply while the power supply is operating in a first mode, the condition being approximately equal to a condition that the power supply would have if the power supply were operating in a second mode. For example, such an apparatus may be able to reduce or eliminate a transient on a regulated output signal (e.g., a regulated output voltage) when a power supply transitions from a first operating mode, such as a pulse-frequency-modulation (PFM) mode, to a second operating mode, such as a pulse-width-modulation (PWM) mode.

Abstract: In an embodiment, a coupled-inductor structure includes first and second windings. The first winding is configured to conduct a phase current, has a first node configured for coupling to a phase node of a power supply, and has a second node configured for coupling to an output node of the power supply and to a first node of a sense impedance that is configured to generate a sense signal representative of the phase current. And the second winding is configured for magnetic coupling with the first winding, has a first node coupled to the first node of the first winding, and has a second node configured for coupling to a second node of the sense impedance. For example, the first winding may be a phase inductor of a switching power supply, and the impedance may be a capacitor that generates a sense voltage representative of the phase current.

Abstract: An embodiment of a power-supply module includes a package having sides, a first power-supply component disposed in the package, and an electromagnetic-interference (EMI) shield disposed adjacent to two sides of the package. For example, such a module may include component-mounting platforms (e.g., a lead frame or printed circuit board) on the top and bottom sides of the module, and these platforms may provide a level of EMI shielding specified for a particular application. Consequently, such a module may provide better EMI shielding than modules with shielding along only one side (e.g., the bottom) of the module. Moreover, if the module components are mounted to, or otherwise thermally coupled to, the shielding platforms, then the module may provide multi-side cooling of the components.

Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.

Abstract: An electronic device that determines an adapter current limit for a power adapter, including a regulator, a voltage comparator, and a controller. The regulator regulates an adapter output current level to prevent it from exceeding the adapter current limit, and provides a regulation signal during regulation. The voltage comparator provides an under-voltage signal when adapter output voltage level falls below a low voltage threshold. The controller initially sets the adapter current limit at a lowest level, increases the adapter current limit by an incremental amount when the regulation signal is provided, and when the under-voltage signal is provided, decreases the adapter current limit by the incremental amount to determine a final adapter current limit. The final adapter current limit is at or near the actual maximum current limit of the power adapter. The adapter current limit may be increased only when regulation occurs for at least a predetermined time period.

Abstract: A hysteretic current mode buck-boost voltage regulator including a buck-boost voltage converter, a switching controller, a window circuit, a ramp circuit, and a timing circuit. The timing circuit may be additional ramp circuits. The voltage converter is toggled between first and second switching states during a boost mode, is toggled between third and fourth switching states during a buck mode, and is sequentially cycled through each switching state during a buck-boost mode. The ramp circuit develops a ramp voltage that simulates current through the voltage converter, and switching is determined using the ramp voltage compared with window voltages provided by the window circuit. The window voltages establish frequency, and may be adjusted based on the input and output voltages. The timing circuit provides timing indications during the buck-boost mode to ensure that the second and fourth switching states have approximately the same duration to provide symmetry of the ramp signal.

Abstract: In an embodiment, a coupled-inductor structure includes first and second windings. The first winding is configured to conduct a phase current, has a first node configured for coupling to a phase node of a power supply, and has a second node configured for coupling to an output node of the power supply and to a first node of a sense impedance that is configured to generate a sense signal representative of the phase current. And the second winding is configured for magnetic coupling with the first winding, has a first node coupled to the first node of the first winding, and has a second node configured for coupling to a second node of the sense impedance. For example, the first winding may be a phase inductor of a switching power supply, and the impedance may be a capacitor that generates a sense voltage representative of the phase current.

Abstract: An embodiment of a power-supply controller includes switching circuitry and an adjuster circuit. The switching circuitry is configured to cause a charging current to flow until the charging current has a predetermined relationship to a threshold, and to cause a discharging current to flow after the charging current. The adjuster circuit is configured to adjust the threshold in response to at least one of a charging period during which the charging current flows and a discharging period during which the discharging current flows. For example, a power supply may include such a power-supply controller to maintain a length of a current pulse, or of a portion thereof, within a particular range, such as approximately at a particular value, during a pulse-frequency-modulation (PFM) mode despite variations in one or more parameters such as input voltage, output voltage, filter capacitance, phase inductance, charging-current-sense impedance, and load, from their respective nominal values.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: An optical proximity detector includes a plurality photodetectors (PDs) and a winner-take-all (WTA) circuit. Each of the PDs has a respective field of view (FOV) and produces a respective analog current detection signal indicative of light incident on and detected by the PD. In an embodiment, the WTA circuit includes a comparator and a multiplexor (MUX). The comparator compares the analog current detection signals produced by the PDs and produces a selection signal in dependence thereon. The MUX receives the analog current detection signals produced by the PDs and outputs one of the analog current detection signals in dependence on the selection signal produced by the comparator. Circuitry, which is shared by the PDs, produces a digital detection signal corresponding to the one of the analog current detection signals output by the MUX. Such design can be used to reduce power consumption, size and cost of an optical proximity detector.

Abstract: An adjustable current-synthesizer may generate synthesized current representative of an actual current, according to a model of a circuit that produces the actual current. The current synthesizer may under-sample a current sense signal derived from the actual current to obtain a few samples of the actual current, which are then used to adjust the synthesized current, thereby ensuring accuracy of the synthesized current. Sample values of the actual current are compared with corresponding generated values of the synthesized current to obtain offset values. In order to maintain monotonicity in the synthesizer results, the offset values are used to make adjustments to the slope of the synthesized current. The slope of the synthesized current may also be adjusted according to the slope of the actual current. Sub-Nyquist sampling of the actual current may be performed on the down-slope, with up-slope adjustments made based on the offset adjustment and down-slope adjustment.

Abstract: A scanning projector system includes a controller, a driver and one or more micro-mirror(s). The controller produces first, second and third pixel data in dependence on a video signal. The driver drives first, second and third light emitting elements in dependence on the first, second and third pixel data, to thereby emit light of first, second and third colors. The micro-mirror(s) project an image in dependence on light beams produced in dependence on the light of the first, second and third colors. The controller controls intensities of the light emitted by the light emitting elements, at least in part, by controlling duty-cycles of pulses included in pixel periods associated with the first, second and third drive signals. To reduce color shifts, the controller and/or the driver causes at least two pulses to be included in each pixel period associated with drive signals used to drive the light emitting elements.

Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.