Abstract: The duration of time during which an AC power voltage sinusoidal waveform remains between negative voltage threshold -V1 volts, nominally 5% of negative peak voltage -V2 volts, and positive voltage threshold +V1 volts, nominally 5% of peak positive voltage +V2 volts, is detected. By the change in voltage with time exhibited by a sinusoidal waveform in the region of zero voltage crossing, the expected time duration between voltage thresholds in approximately 5% of one-half period of such sinusoidal waveform. If the actual time between voltage thresholds exceeds (nominally) twice this value, or 10% of one-half period, then a power black-out condition is sensed, and a power fault signal is produced.

Abstract: The invention performs the multiplication and/or accumulation of digital numbers in either two's complement of unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.

Abstract: A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.

Abstract: A power supply switching circuit is disclosed which provides for automatically switching an electrical circuit load from a main power source to an auxiliary power source, yet maintains the two power sources isolated from each other. The power supply switching circuit is readily integrated with its electrical load to form a monolithic integrated circuit. A pair of MOSFETs provides alternate connections of the load to the respective power sources. The circuit effectively connects the gate and source of the appropriate MOSFET across the available power source and thus assures the maximum turn-on voltage is applied to the MOSFET.

Abstract: A parallel EXCLUSIVE or and EXCLUSIVE NOR gate comprising four tri-inverter circuits in which the input transistors of the tri-inverter circuits are shared.

Abstract: A high frequency CMOS voltage level shifter providing either an inverted or noninverted signal output shifted in voltage level from an input signal. The level shifter includes two pairs of metal oxide semiconductor transistors with the transistors of each pair connected together and respectively connected to a first and second voltage source. The gates of a transistor in each pair are cross connected to the interconnected drains of the opposing transistor pair. First and second conducting elements are respectively connected to the cross connected transistor gates to discharge a transient capacitive gate charge present during output signal voltage level shifting.

Abstract: A power supply regulator in which a control pulse is generated at a position in time which varies in accordance with the voltage or current supplied by the power supply. The control pulse can be fed back across an isolation boundary with a simple device such as a pulse transformer with little or no loss of accuracy. Such a control signal is particularly adaptable to varying the duty cycles of transistor switch drive signals for switched-mode power supplies.

Abstract: A power field-effect transistor device includes a source electrode metallization layer having windows to reduce interlayer capacitance and shorting between the source electrode and gate electrode layers. An alternative embodiment has source bus expanded areas for accommodating the source electrode layer contacts, which are orthogonally placed to facilitate the construction of the device.

Abstract: An operational amplifier or comparator is provided in which internal parasitic capacitances are buffered to increase the gain bandwidth product of the amplifier.

Abstract: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

Abstract: A charging circuit is provided to decrease the settling time of a reference capacitor storing a reference voltage for data acquisition circuits. The charging circuit includes one or more comparator circuits for comparing the voltage across the reference capacitor to the reference voltage provided by a reference source. If the voltage from the reference source deviates by a predetermined amount, one or more buffer circuits rapidly charge the reference capacitor to a voltage substantially equal to the new reference voltage. The reference source is then coupled directly to the capacitor to complete the charging of the capacitor to the new reference voltage.

Abstract: Conversion is achieved by subdividing the intergrate and deintegrate periods into a plurality of integrate and deintegrate phases. Power frequency rejection can be maintained by defining the combined integrate phases to integrate over at least one complete power line cycle. Sychronization of the integrate phases with the power line cycle is maintained by separating integrate phases with a combined deintegrate and rest phase of fixed duration.

Abstract: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

Abstract: An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.

Abstract: A programmable interface to selectively couple the terminals of an electronic system to desired circuit locations within the system. By applying programming signals to the input terminals of the interface in a prescribed sequence, the interface is programmed so that subsequently applied control signals will be coupled to the desired circuit locations. The function served by each terminal thus depends on the programming sequence. Reprogramming can change the function of each of the terminals by coupling them to different circuit locations.

Abstract: An improved analog to digital converter in which an approximate digital representation is provided by a parallel analog to digital converter and the conversion is completed by a successive approximation analog to digital converter.

Abstract: An improved analog to digital converter is provided in which high and low order bytes of the digital output can be sequentially generated by a single flash converter circuit. Upon the generation of the high order byte, a high byte equivalent voltage is subtracted from the analog input voltage and the residual is multiplied by a predetermined factor. The resultant product signal is converted by the same flash converter circuit to the low order byte. In addition, the low scale and full scale of the converter inputs may be programmed to have the same polarity as, or the opposite polarity of, the polarities of the reference voltages.

Abstract: A dual slope analog-to-digital converter with automatic short cycle range determination. The time period of the signal integrate phase is adjusted to accommodate different ranges of input signals. Range selection is achieved automatically with the converter switching quickly from one range to another until the right range is found, without the necessity of displaying an "out of range" reading. Normal mode rejection of 60 Hz noise is achieved on all timing ranges.

Abstract: A load circuit is provided with a backup power supply to power the essential functions of the load in the event that its primary power supply fails or is otherwise degraded. The positive terminals of both the primary power supply and the backup power supply, having a common negative reference, are input to a differential voltage comparator circuit. The output of the differential voltage comparator circuit controls a switching transistor located in a line between the primary power supply and the load, and when inverted by an inverter circuit, controls a second switching transistor located in a line between the backup power supply and the load. In operation, only the more positive of the primary power or the backup power supply voltages is provided to the load. The output of the inverter circuit is also available to indicate which of the two sources the power is applied to the load, and may be further used to disable non-essential portions of the load circuitry.

Abstract: An analog to digital converter is provided in which the converter output is scaled in accordance with the ratio of the clocking frequencies.