Abstract: An integrating type analog-to-digital converter with improved time measurement capabilities and a very fast conversion cycle. The converter operates by integrating an analog input signal for a predetermined time period and then deintegrating the integrated signal until its output crosses zero. The time it takes for the integrator to cross zero is measured by a digital clock, and the zero crossing is detected as occurring on the first clock pulse after the integrator output has actually crossed zero. The residual output of the integrator at the point of detection is multiplied by a predetermined negative amount and fed back so that the integrator output assumes the multiplied value of the residual. The integrator is then deintegrated for a second time and the time it takes for the integrator output to pass zero is again measured by the clock. The measured time is proportional to the error in the measurement between the detected zero crossing and actual zero crossing in the initial deintegration cycle.

Abstract: A high speed charge balancing comparator in which, without loading or affecting its input, the internal nodes and output node are maintained at voltage levels at or very close to their autozero values until a time after the commencement of the compare phase such that the polarity of the voltage at the input charge balancing node is correct. The comparator is of the type for comparing two or more voltages including a gain stage having an input node responsive to the voltages, plural internal nodes and an output node, and a plurality of switches for sequencing the voltages to the input nodes during alternate autozero and compare phases. Switches maintain the gain stage internal nodes and output node at voltage levels close to their values during the autozero phase until a time after the commencement of the compare phase.

Abstract: A digitally switched analog signal conditioner comprising a plurality of pairs of input terminals, a junction, and an output terminal; a plurality of capacitors, first ends of the capacitors being connected to the junction; a plurality of switches being arranged in pairs, first ends of each pair being connected to the other ends of different ones of the capacitors, the other ends of each pair being connected to respective ones of a pair of input terminals, the switches of each pair being adapted to be operated alternatively; an amplifier having an input and an output, the input being operatively coupled to the junction; and a sample and hold circuit operatively coupled to the output of the amplifier for periodically sampling and holding the output, the output of the sampling and holding circuit being connected to one of the input terminals of one of the pairs of input terminals, the other of the terminals of the one pair of input terminals being connected to a point of reference potential.

Abstract: Apparatus for detecting, in advance, by a desired length of time, the imminent failure of electric output power provided by an electric power supply due to the reduction or loss of input power. The magnitude of the voltage on an energy storage reservoir capacitor is monitored for deriving a voltage signal proportional to the rate of change thereof. The rate of change voltage is multiplied by a voltage proportional to a desired early warning time interval and this product is added to a voltage proportional to a minimum value of voltage on the capacitor, thus representing an amount of stored energy sufficient to sustain normal output power for a desired time interval. The voltage derived by the adding means is compared with the voltage on the energy storage capacitor for signalling imminent power supply failure when the compared voltages are equal.

Abstract: A class AB CMOS amplifier having a particular circuit configuration and useful in a variety of products such as operational amplifiers, chopper stabilized amplifiers, commutating autozero amplifiers and the like.

Abstract: A CMOS digital level shifter circuit is provided which latches one transistor of a complementary transistor pair off when the other transistor of the pair is on to prevent direct current dissipation of power when the input signals to the shifter circuit are not in transition.

Abstract: A circuit which accepts an input signal of either positive or negative polarity and produces an output signal having an open circuit voltage similar in amplitude to the input signal amplitude but having a defined polarity. A plurality of switching elements, preferably MOS transistors, are connected in a bridge circuit, the bridge circuit having a pair of input terminals responsive to the input signal and a pair of output terminals for providing the output signal, the switching elements being connected between the input and output terminals. Each of the switching elements has a control input connected to one of the input terminals whereby each of the switching elements automatically opens or closes in response to the polarity of the input signal to maintain the defined polarity of the output signal.

Abstract: An improved field terminating structure for a semiconductor device provides a well defined voltage gradient in the vicinity of a p-n junction to reduce the electric field near the junction and increase the junction breakdown voltage. The structure includes one or more MOS-type field effect transistors operably connected to one of the regions of the junction. A portion of the potential difference applied across the junction corresponding to the threshold voltage of each transistor is distributed across the surface of the device near the junction.

Abstract: A high accuracy monolithic digital to analog converter (DAC) which employs an EPROM controlled correction DAC to correct for errors in the output of a primary DAC. The correction DAC empolys a non-binary bit weighting which permits the use of low accuracy components in the fabrication of the correction DAC. The output of the primary DAC is skewed so that the required correction is always in a single direction, thereby eliminating the need for a constant offset generator. Resistors necessary for bipolar operation are included on the chip, thereby eliminating the need for connection of any external resistors to achieve such operation.

Abstract: A semiconductor device is provided comprising a monolithically merged field-effect transistor and bipolar junction transistor. The device has a semiconductor region with a base contact and a gate electrode such that a signal applied to the base contact causes the device to function as a bipolar junction transistor, while a signal applied to the gate electrode causes the device to function as a field-effect transistor. In this manner, the mode of operation may be chosen so as to achieve the most desired operating characteristics.

Abstract: An operational amplifier is provided having two input legs and a reference leg. In order to eliminate any input offset voltage between the two input legs, the reference leg is balanced against the first input leg and then against the second input leg so that the first input leg is thereby balanced against the second input leg and any offset voltage is significantly reduced or eliminated.

Abstract: An integrating type analog-to-digital converter with improved time measurement capabilities and a very fast conversion cycle. The converter operates by integrating an analog input signal for a predetermined time period and then deintegrating the integrated signal until its output crosses zero. The time it takes for the integrator to cross zero is measured by a digital clock, and the zero crossing is detected as occurring on the first clock pulse after the integrator output has actually crossed zero. The residual output of the integrator at the point of detection is multiplied by a predetermined negative amount and fed back so that the integrator output assumes the multiplied value of the residual. The integrator is then deintegrated for a second time and the time it takes for the integrator output to pass zero is again measured by the clock. The measured time is proportional to the error in the measurement between the detected zero crossing and actual zero crossing in the initial deintegration cycle.

Abstract: In this successive approximation analog-to-digital converter non-precise impedance elements are used in a circuit which provides successive analog step values that approximate a non-binary series in which (above a certain minimum) each term is smaller than the sum of the preceding series terms. The actual values of the analog quantities that are produced by the corresponding individual impedance elements are stored in digital format in a memory. These quantities are measured and stored with an accuracy which exceeds the accuracy expected for the final operation of the system. At each conversion step, the unknown analog input is compared with the sum of a pair of step values, the smaller of which is greater than the maximum expected comparator error. An acceptable comparator output may be obtained before the comparator has completely settled.

Abstract: A voltage tripler for multiplying a DC voltage from a battery to provide a driving voltage for an LCD display in a digital clock. The circuit includes a charging capacitor and two storage capacitors and a plurality of switches for interconnecting the capacitors with the battery. The switches are controlled by means of driving circuitry which provides break-before-make type switching. The operation of the circuit is divided into four phases. During an initial phase the charging capacitor is charged to the voltage of the battery. During the second phase the charging capacitor is connected in parallel with one of the storage capacitors in order to transfer a portion of the charge to the storage capacitor. During the third phase the charging capacitor is again connected to the battery to recharge the charging capacitor. During the fourth phase, the charging capacitor is connected in parallel with the other storage capacitor so as to transfer charge to the storage capacitor.

Abstract: A system or circuit for signal level translation by information storage on multiple capacitors subjected to commutation at a frequency higher than the highest preserved frequency component of the signal. Continuous level translation of information, such as successive voltage levels, is accomplished with very small error. The invention is particularly applicable to instrumentation amplifiers for example, wherein differential input voltages are required to be referenced to some other base voltage such as zero or ground voltage.

Abstract: An active analog signal processing system preferably embodied as an integrated circuit includes a pair of like amplifiers which are alternately switched between a first signal processing mode and a second zeroing mode in which a capacitor in the amplifier circuit is reverse charged to a voltage level equivalent to the average noise voltage level of the system whereby the system automatically cancels the low frequency noise thereof to provide a simple low noise processing system.

Abstract: An integrated circuit aluminum-silicon electrical contact may be fabricated in a diffusion region formed in a monocrystalline silicon semiconductor layer by converting the upper portion of the diffusion region into an amorphous region. Alloy pitting is substantially decreased since the solubility of silicon in aluminum is highly dependent upon crystallographic orientation of the silicon and decreases as the silicon approaches an amorphous form. The amorphous region may be formed by implanting arsenic ions with an energy of at least 180 keV and a dosage of approximately 10.sup.15 ions/cm.sup.2.

Abstract: A buried load device in an integrated circuit extends between two regions of like conductivity isolated from each other by thick oxide and substrate comprises a channel beneath the oxide and having dimensions defined by a diffused region of opposite conductivity type. The buried channel is formed by impurity migration from an upper epitaxial layer that is oxidized to separate two regions and the connecting channel width is defined by diffused strip regions of opposite conductivity to establish a desired current-voltage relationship thereof.

Abstract: A system for digitally displaying watch functions and setting the value of these functions with a single actuator button wherein the button is movable to establish a first mode of operation to sequentially display the watch functions and is alternatively movable to establish a second mode of operation wherein the button may be employed to set or adjust the digital readout.

Abstract: A subminiature switch structure particularly adapted for cooperation with integrated circuits as may, for example, be employed in an electronic watch including a restrained spring wire manually movable by resilient bending from normal spring loaded engagement with a first terminal into wiping engagement with a second terminal.