Patents Assigned to Invarium, Inc.
  • Publication number: 20110154281
    Abstract: A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: Invarium, Inc.
    Inventor: Franz Xaver Zach
  • Patent number: 7444615
    Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: October 28, 2008
    Assignee: Invarium, Inc.
    Inventors: Gokhan Percin, Ram S. Ramanujam, Franz X. Zach, Abdurrahman Sezginer, Chi-Song Horng, Roy Prasad
  • Patent number: 7401319
    Abstract: A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: July 15, 2008
    Assignee: Invarium, Inc.
    Inventors: Chi-Song Horng, Devendra Joshi, Anwei Liu
  • Patent number: 7392502
    Abstract: This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: June 24, 2008
    Assignee: Invarium, Inc.
    Inventors: Gökhan Percin, Ram Ramanujam, Franz Xaver Zach, Koichi Suzuki
  • Patent number: 7379170
    Abstract: A system and method for characterizing an imaging system causes a diffraction image indicative of a test structure having a generalized line-grating to be formed and then extracts from a measurement of the diffraction image a lens transmittance function, a photoresist property or a defocus distance.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: May 27, 2008
    Assignee: Invarium, Inc.
    Inventors: Hsu-Ting Huang, Abdurrahman Sezginer
  • Patent number: 7318214
    Abstract: The present invention provides a system and method of modifying the mask layout shapes of an integrated circuit layout design to compensate for reticle field location-specific systematic CD variations resulting from mask writing process variations, lens imperfections in lithographic patterning, and photoresist process variations. Called PLC (Process-optimized Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular mask-writer-patterning-tools-and-resist-process combination, and are performed on a reticle-wide basis. Furthermore, for each geometric shape in the mask layout, the amount of modification is determined based on a categorization of the type of the shape, the specific location in the reticle field the particular shape falls in, its context (i.e., surrounding patterns, orientation, etc.), as well as certain photoresist parameters to be used in the patterning process.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: January 8, 2008
    Assignee: Invarium, Inc.
    Inventors: Roy V. Prasad, Chi-Song Horng, Ram S. Ramanujam
  • Patent number: 7277165
    Abstract: A method of measuring flare in an optical lithographic system utilizes an exposure mask with first and second discrete opaque features each having rotational symmetry of order greater than four and of different respective areas. The exposure mask is positioned in the lithographic system such that actinic radiation emitted by the lithographic system illuminates the sensitive surface of an exposure target through the exposure mask. The extent to which regions of the sensitive surface that are within the geometric image of a feature of the exposure mask are exposed to actinic radiation during due to flare is measured.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: October 2, 2007
    Assignee: Invarium, Inc.
    Inventors: Bo Wu, Abdurrahman Sezginer
  • Patent number: 7275225
    Abstract: A method of correction for design data includes the steps of sequentially applying a plurality of corrections to a plurality of features based on a plurality of feature tolerances to design data in a predetermined order, and providing corrected design data.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: September 25, 2007
    Assignee: Invarium, Inc.
    Inventor: Vishnu G. Kamat
  • Patent number: 7266800
    Abstract: Computational models of a patterning process are described. Any one of these computational models can be implemented as computer-readable program code embodied in computer-readable media. The embodiments described herein explain techniques that can be used to adjust parameters of these models according to measurements, as well as how predictions made from these models can be used to correct lithography data. Corrected lithography data can be used to manufacture a device, such as an integrated circuit.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: September 4, 2007
    Assignee: Invarium, Inc.
    Inventor: Abdurrahman Sezginer
  • Patent number: 7246343
    Abstract: A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the other instances of the repeating cluster based on their positions in the exposure field. Or, optical proximity corrections can be applied to the repeating cluster of objects for different values of flare intensity, or another parameter of patterning imperfection, such as by calculating the value of the flare at the location of each instance of the repeating cluster, and interpolating the optical proximity corrections to those values of flare.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 17, 2007
    Assignee: Invarium, Inc.
    Inventors: Devendra Joshi, Abdurrahman Sezginer, Franz X. Zach
  • Patent number: 7224437
    Abstract: An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: May 29, 2007
    Assignee: Invarium, Inc
    Inventors: Gökhan Perçin, Abdurrahman Sezginer, Franz Xaver Zach
  • Patent number: 7189481
    Abstract: Flare of an imaging system is measured using resist by employing the imaging system to directly expose a first part of the resist at an image plane of the imaging system to a first dose of radiation and to indirectly expose a second part of the resist as a result of flare. The imaging system exposes the second part of the resist to a second dose of radiation. Flare of the imaging system is determined from a pattern that is formed in the second part of the resist.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: March 13, 2007
    Assignee: Invarium, Inc.
    Inventors: Bo Wu, Abdurrahman Sezginer, Franz X. Zach
  • Publication number: 20060282814
    Abstract: A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures to be measured and to obtain at least one computational model for optical proximity correction purposes.
    Type: Application
    Filed: May 31, 2005
    Publication date: December 14, 2006
    Applicant: Invarium, Inc.
    Inventors: Gokhan Percin, Ram Ramanujam, Franz Zach
  • Publication number: 20060268254
    Abstract: An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.
    Type: Application
    Filed: May 31, 2005
    Publication date: November 30, 2006
    Applicant: Invarium, Inc.
    Inventors: Gokhan Percin, Abdurrahman Sezginer, Franz Zach
  • Publication number: 20060251994
    Abstract: A system and method for characterizing an imaging system causes a diffraction image indicative of a test structure having a generalized line-grating to be formed and then extracts from a measurement of the diffraction image a lens transmittance function, a photoresist property or a defocus distance.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 9, 2006
    Applicant: Invarium, Inc.
    Inventors: Hsu-Ting Huang, Abdurrahman Sezginer
  • Publication number: 20060248497
    Abstract: An apparatus and method of compensating for lens imperfections in a projection lithography tool, includes extracting from a diffraction image created by the projection lithography tool a lens transmittance function, and then using the extracted lens transmittance function as a compensator in the lithography projection tool. Another preferred apparatus and method of synthesizing a photomask pattern includes obtaining a phase and an amplitude of a transmittance function of an imaging system; forming a computational model of patterning that includes the transmittance function of the imaging system; and then synthesizing a mask pattern from a given target pattern, by minimizing differences between the target pattern and another pattern that the computational model predicts the synthesized mask pattern will form on a wafer.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 2, 2006
    Applicant: Invarium, Inc.
    Inventors: Hsu-Ting Huang, Abdurrahman Sezginer
  • Publication number: 20060248499
    Abstract: A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in the figure-of-demerit, wherein disrupting polygons includes any of the following polygon disruptions: breaking up, merging, or deleting polygons.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 2, 2006
    Applicant: INVARIUM, INC.
    Inventors: Abdurrahman Sezginer, Roy Prasad
  • Publication number: 20060248495
    Abstract: An apparatus and method for improving image quality in a photolithographic process includes calculating a figure-of-demerit for a photolithographic mask function and then adjusting said photolithographic mask function to reduce the figure of demerit.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 2, 2006
    Applicant: Invarium, Inc.
    Inventor: Abdurrahman Sezginer
  • Publication number: 20060248498
    Abstract: An apparatus and method of synthesizing a photolithographic data set includes using a first computational model to calculate a first figure-of-merit for the photolithographic data set; changing a first part of the photolithographic data set to increase the first figure-of-merit; and then using a second computational model to calculate a second figure-of-merit of the photolithographic data set; and changing a second part of the photolithographic data set to increase the second figure-of-merit. The second computational model enables figure-of-merit calculations to be executed at a significantly faster execution rate that the first computational model.
    Type: Application
    Filed: August 13, 2005
    Publication date: November 2, 2006
    Applicant: Invarium, Inc.
    Inventors: Abdurrahman Sezginer, Roy Prasad, Chi-Song Horng, Hsu-Ting Huang
  • Publication number: 20060236271
    Abstract: A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.
    Type: Application
    Filed: April 9, 2005
    Publication date: October 19, 2006
    Applicant: Invarium, Inc.
    Inventor: Franz Zach