Abstract: Neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. The following benefits are obtained: (1) The starting IC chips (die) intended for stacking may have different sizes, and serve different electronic purposes. After they are encapsulated in same-size neo-chips, they can be efficiently stacked using well-developed processing steps; (2) The individual chips for stacking can be purchased as "known good" die.

Abstract: A self-aligning optical beam system is disclosed in which optical alignment of two beam-carrying portions, such as a laser beam generated by a chip, and a light guide formed as a waveguide in a polymeric material, is precisely controlled by plug-and-socket connection between a substrate and a chip. Plugs in the form of solder bumps are formed on one surface of a laser chip, and are inserted in sockets provided in a substrate. The optical alignment is precisely controlled in three axes, two of which guarantee alignment for laser beam transmission into a waveguide, and one of which minimizes the gap across which the beam travels.A powerful waveguide division multiplexer may be provided by having numerous converging waveguides on a single substrate, and by stacking a number of substrates, all of whose waveguides feed into a single optical output channel.

Abstract: Stacked, multimodular circuit assemblies are provided which comprise stacked, resealable, modules containing electronic circuitry, each module having a plurality of electrically conductive, embedded through-vias between the upper and major surfaces thereof. The through-vias are contained within the module matrix outside of the circuit-containing cavity or "tub" of the module and within the outer edges of the module body. Electronic circuitry contained in the module cavity is electrically connected to the through-vias by signal traces or vias passing out of the cavity and into contact with the through-vias, and adjacent modules are electrically interconnected by a resealable, multichannel connector array between adjacent modules having electrically conductive channels coupling opposing through-vias of the adjacent modules.

Abstract: A process in which a plurality of IC chips are stacked in a unitary structure having a novel method of exposing leads on the access plane of the stack. After a layer of dielectric material has been formed on the access plane, trenches (preferably trenches) are formed, e.g., by wet lithographic processing, which expose the access plane leads. Thereafter terminals are formed on the access plane in contact with the leads. At the wafer level, layers of dielectric material are deposited which are sufficiently thick to permit the subsequent forming of trenches in the access plane dielectric without uncovering any of the silicon of the IC chips.

Abstract: Circuitry for sensing a relatively large number of events, and outputting to processing circuitry only those events which have two characteristics: (1) a magnitude above a preselected threshold level, and (2) a rate of change greater than a preselected background rate of change. Logic circuitry is used to assign any event which has the desired characteristics to an available output channel. Subtracter circuitry causes the background to be subtracted from the sensing input, in order to limit the output to non-background events.

Abstract: An electronic package is disclosed in which a plurality of stacked "same function" IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is "unaware" that substitution has been made. Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips. In order to "translate" signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips. Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry. Additionally, the VIC chip should provide power supply buffering.

Abstract: A wireless infrared pulse-transmitting system for communication with electronic components. The receiver for such a system has radically reduced current (and power) values, which permit a battery-powered receiver to remain on while awaiting transmitter signals. Use of several mosfet transistors operating in the subthreshold region minimizes power. Bandwidth requirements are met, in spite of the low power operation. In order to eliminate amplifier saturation, with the accompanying problem of recovery time which slows the transmission process, clamping circuitry is used to cause instantaneous shunting of signals when a predetermined signal level is reached.

Abstract: An electronic module comprising a multiplicity of prestacked IC chips, such as memory chips, and an IC chip, referred to as an active substrate or active backplane, to which the stack of chips is directly secured. A multiplicity of aligned solder bumps may interconnect the stack and the substrate, providing electrical, mechanical and thermal interconnection. The active substrate is a layer containing substantial amounts of integrated circuitry, which interfaces, on one hand, with the integrated circuitry in the stacked chips, and, on the other hand, with the external computer bus system. Some of the high priority circuitry which may be included in the substrate is used for control, fault-tolerance, buffering, and data management.

Abstract: A tool for segmenting a stack of bonded IC chips into short stacks includes a heat conducting base having at least one cavity in its upper face for receiving a portion of an IC chip stack. The length and width dimensions of the cavity are essentially the same as the corresponding dimensions of the stack. The depth of the cavity is selected to correspond to the desired thickness of the short stack to be formed from the stack. The base is heated to raise the temperature of the cavity walls to heat the stack above the softening point of the bonding material. A driver is movably mounted on the base for contact with a portion of a face of the stack extending above the opening of the cavity, and a threaded rod supported on the base urges the driver against the stack to effect separation of the extending portion of the stack from the segment portion which remains in the cavity. A track in the upper surface of the base is provided for travel of the driver.

Abstract: An integrated stack of layers incorporating a plurality of IC chip layers has an end layer which is formed of dielectric material (or covered with such material). The outer surface of the end layer provides a substantial area for the spaced location of a multiplicity of lead-out terminals, to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal on the outer surface of the end layer is connected to IC circuitry embedded in the stack by means of conducting material in a hole through the end layer, and a conductor (trace) on the inner surface of the end layer which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metalization on the access plane face of the stack.

Abstract: A method and product are disclosed in which multiple solder bumps on a first planar surface are guided into engagement with terminals on a second planar surface by means of holes formed (by a photolithographic process) in a dielectric layer, which has been added to the second surface to provide the holes (or sockets) through which the solder bumps (or plugs) extend. The perforated (hole-providing) layer may be formed of one of several materials. The preferred perforated layer material is a photo-definable polyimide, which is hardened by heating after the holes have been formed. Small solder bumps may be formed inside the holes on the second surface, in order to facilitate bonding between the solder bumps on the first surface and the terminals on the second surface.

Abstract: A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Abstract: In accordance with the invention a system is described for controllably varying the resolution of an image event to conserve data output by varying the size of the instantaneous IFOV of an array of detectors. The system comprises a multiplicity of individual detectors which produce an electrical signal in response to an image stimulus. The detectors are connected to busing circuitry by a circuit associated with each individual detector and which is in parallel with the circuits from the other detectors. Each parallel circuit includes a switch for making and breaking the parallel circuit to the busing circuit and control means are provided for opening and closing the switches in real time. As the switches are opened and closed the output signals of the detectors are combined into signals representing pixels having various size instantaneous fields of view depending on the number of detectors whose signals are combined.

Abstract: A method for fabricating stacks of IC chips into modules providing high density electronics. A relatively large number of layers are stacked, and then integrated by curing adhesive applied between adjacent layers. A large stack is formed, various processing steps are performed on the access plane face of the large stack, and then the large stack is segmented to form a plurality of smaller, or short, stacks. Means are provided for causing separation of the larger stack into smaller stacks, without disturbing the adhesive which binds the layers within each small stack.

Abstract: This application discloses hardware suitable for use in a neural network system. It makes use of Z-technology modules, each containing densely packaged electronic circuitry. The modules provide access planes which are electrically connected to circuitry located on planar surfaces interfacing with such access planes. One such planar surface comprises a resistive feedback network. By combining two Z-technology modules, whose stacked chips are in planes perpendicular to one another, and using switching networks between the two modules, the system provides bidirectional accessibility of each individual electronic element in the neural network to most or all of the other individual electronic elements in the system.

Abstract: A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips.

Abstract: An integrated circuit chip having a plurality of parallel channels, and a stack of such chips, are disclosed, in which the function of A/D signal conversion is accomplished in each on-chip channel. In order to satisfy the power and real estate limitations of the chip(s), a substantial part of the A/D conversion circuitry is located off-chip. Two devices are required in each channel on each chip, a precision comparator, and a storage register. These may be combined with an off-chip analog ramp, and an off-chip digital ramp. Certain on-chip performance enhancements are disclosed, which can operate either in the analog mode or the digital mode. One such enhancement is compensating for the voltage offset of each comparator. Another enhancement is reducing the duty cycle of each precision comparator, in order to lower power requirements. An important use for the disclosed concepts is the field of multi-layer Z-technology modules, having two dimensional photo-detector arrays.

Abstract: A high-density electronic module is disclosed, which is suitable for use as a DRAM, SRAM, ROM, logic unit, arithmetic unit, etc. It is formed by stacking integrated-circuit chips, each of which carries integrated circuitry. The chips are glued together, with their leads along one edge, so that all the leads of the stack are exposed on an access plane. Where heat extraction augmentation is needed, additional interleaved layers are included in the stacks which have high thermal conductivity, and are electrical insulators. These interleaved layers may carry rerouting electrical conductors. Bonding bumps are formed at appropriate points on the access plane. A stack-supporting substrate is provided with suitable circuitry and bonding bumps on its face. A layer of insulation is applied to either the access plane or stack-supporting substrate, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied.

Abstract: A bump bonding process and product are disclosed in which both pressure and heating are used in situations where the temperature should not exceed a predetermined amount, e.g., bonding of a photoconductor array to a module containing electronic processing devices. The bonding process involves eutectic alloying of indium and bismuth, allowing welding of the bumps at a temperature substantially below the two metals' melting points. In one version of the invention, bumps on adjacent substrates are directly aligned. In another version, each bump on one substrate is wedged between a pair of bumps on the other substrate.

Abstract: A multiplexer circuit is disclosed, for use with such signal sources as focal plane detector arrays, which contains a large number of parallel branches, each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier. The amplifier in each branch receives high impedance voltage signals orginating from its individual detector and converts them with high power gain into current signals which feed into the common output line whenever the switch in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a signal IC chip which provides CMOS logic.