Abstract: The control unit is arranged to handle the requests for transmission and reception interrupts (i.e. requests to the central logic unit CPU to halt its operative program in order to transmit or receive messages to or from a peripheral unit) in arrival from the input/output interface circuits, each of which is associated with a peripheral unit. To this purpose, the interface circuits are cyclically scanned to groups of n: the presence of at least one interrupt request halts the scanning and causes a request criterion to be transmitted to the central logic unit (CPU) by the control unit. The address of the peripheral unit presenting the highest priority among those of the group requiring an interrupt is written into the state register of the control unit, the address being composed of the number of the group (supplied by the scanner) and by the code generated by a priority coder.

Abstract: Two identical processors of a communication system, operating in master-slave relationship, each have a mass memory, a working memory, a CPU and an interface interlinked by an internal bus, the two interfaces being interconnected by an interprocessor bus serving for the exchange of data therebetween. When the mass memory of the slave process or needs updating, data words to be transferred from the mass memory of the master processor are fed via the interprocessor bus and a buffer store of the slave processor to the working memory thereof from which they are subsequently delivered to the associated mass memory while the CPU of the master processor performs other operations. A block of data words thus transferred is preceded by a header, emitted by the master CPU, which sets a word counter in the associated interface whose progressive decrementation determines the end of the transfer operation.

Abstract: A circuit arrangement for detecting the error rate (BER) in numerical transmission systems which use a line code of the 1B/2B type. The circuit arrangement includes the presence of means (MS) to output respectively a first and a second bit stream (A and B) obtained by serializing respectively the first and the second bits of the words making up the input stream. The streams (A and B) are input respectively into the first and second means for detecting errors (PRE and SRE) designed to activate their own outputs when they detect the presence of pairs of bits that are respectively "1--1" and "0--0". Furthermore, it includes the presence of error-totalling means (TE) connected to the outputs of the first and second means for detecting errors.

Abstract: A plurality of switching modules, e.g. components of a digital telephone exchange, each include a pair of central processing units (CPUs) operating in master-slave relationship under the supervisory control of two support processors alos constituting a master-slave pair. Each support processor communicates via a respective bus with all switching modules by way of respective signal lines extending from that bus to one CPU of each pair. Each signal line includes two closely juxtaposed, cascaded interfaces each of which, in turn, has an externally and an internally accessible input/output (I/O) section. The externally accessible I/O section of each interface inserted in the active line between the master processor and the master CPU of any module is normally operational and communicates by an in-line link with the corresponding I/O section of the interface in cascade therewith.

Abstract: The loop uses a phase comparator (PD) designed to compare the phase of a reference signal (F.sub.1) with the phase of a signal generated locally (F.sub.2) and also to make available on a first output (E) a signal expressing the entity of phase shift and on a second output (S) a signal expressing the sign of the phase shift (F.sub.1 leading, or lagging, in respect to F.sub.2). Thanks to the presence of this latter signal (S) it is possible to render the remaining units of the loop particularly simple and economic without having to make use of components that introduce in their turn limits in operational speed, excepting of course those imposed by the type of technology used. This loop is suitable to be conveniently implemented in an integrated manner.

Abstract: A plurality of routing modules in a switching network of a telecommunication system each includes several interfaces connected to a first channel concentrator via respective data stores receiving and temporarily memorizing incoming data words coding the voltage levels of message samples from associated peripheral units served by the respective interface. In response to commands from a control unit, included in the module, this first concentrator selectively transmits memorized data words in respective phases of a PCM frame to all the modules in the network. Outgoing data words issuing from any routing module are registered in other data stores and selectively extracted therefrom by a second channel concentrator under instructions from the control unit, the extracted data words being distributed by a channel expander commanded by the control unit to registers assigned to respective peripheral units.

Abstract: A network for selectively switching channels from n incoming PCM links to as many outgoing PCM links comprises two sections of a receiving-side stage with n input terminals each, connected in parallel to respective incoming links, and with m output terminals working into an intermediate stage with 2m input terminals and as many output terminals. The latter are connected to respective input terminals of two sections of a transmitting-side stage with n output terminals each; homologous output terminals of the two transmitting-side sections are alternatively connectable to respective channels of n outgoing PCM links by means of multiplexers which are switched by a logic unit under the control of a processor also detecting possible malfunctions in any section. Each stage consists of a multiplicity of temporal or spatial switching matrices.

Abstract: A digitally operating telephone exchange or central office comprises at least one elemental switching assembly AC including a multiplicity of routing modules MII interconnected by PCM lines FII, each module communicating directly with one or more interfaces UAA, TNN, UGG which provide some of these modules with access to subscriber lines, other of these modules with access to digital trunks extending to remote exchanges, and still other modules with access to analog-type trunks. The operations of the routing modules MII and the digital-trunk interfaces TNN are controlled by a common supervisory processor SGS and are timed by a central clock CKC. A centralized oscillator GC supplies the line interfaces UAA with ringing current and with an audio-frequency carrier modulable for signalization purposes.

Abstract: A telecommunication system, e.g. a telephone switching exchange, comprises a multiplicity of substantially identical modular units each including a microprocessor controlling the emission of departing digital messages by a transmitting section and handling arriving digital messages reaching a receiving section. Each modular unit is connected to all other units by an outgoing and an incoming two-wire line each including a signaling wire and a response wire. The signaling wire of the outgoing line of a given modular unit emits, in the presence of a departing message in a memory of the associated transmitting section, a data-ready signal to the receiving section of the modular unit for which that message is destined; the latter section, continuously scanning the signaling wires of all incoming lines, then halts its scan and sends back an acknowledgement signal on the response wire of the same line whereupon the message is sent out on the aforementioned signaling wire.

Abstract: A circuit component for separating and/or combining two pairs of high-frequency signal waves lying in different frequency bands, the waves of each pair having the same frequency but mutually orthogonal planes of polarization, comprises two mutually identical and aligned 3dB couplers bracketing a filtering assembly between them. Each 3dB coupler has a central guide of square cross-section surrounded by four collateral guides, each connected with the central guide by a coupling guide letting only the waves polarized in one plane--regardless of frequency--pass therebetween. The filtering assembly has sets of baffles in line with the central and collateral guides of both couplers, these baffles defining slots giving passage to only the waves of one of the two bands while reflecting the others.

Abstract: Two intercommunicating functional units, namely a master unit such as a processor and an associated peripheral or slave unit, exchange 32-bit messages--with 24 information bits followed by 8 cyclic redundancy bits--by way of a control unit and upon initiation by the master unit. A receiving section of each functional unit includes a redundancy generator which, on the basis of the information bits of an incoming message, recalculates the redundancy bits in accordance with a predetermined polynomial code and sends the result to the control unit which has a similar redundancy generator responsive to the information bits of a transiting message for recalculating the same redundancy bits. The control unit compares the locally generated redundancy bits with those of the transiting message and those sent back from the message-receiving unit; in the event of a discrepancy, it identifies one or the other functional unit as the site of a detected error.

Abstract: A layer of dielectric material, carrying printed or thick-film circuit components on opposite surfaces, is provided with one or more bores extending between aligned circuit points to be conductively interconnected. The layer is sandwiched between two masks having a perforation of larger diameter in line with each bore, such perforation communicating with a respective chamber in an adjoining member forming part of a pair of clamp jaws pressing the masks against the layer. A conductive liquid or paste in one chamber is pumped through each bore from one chamber into the other, via the adjoining perforations, by the respective application of pressure and suction to these chambers with the aid of membranes or pistons moving codirectionally in one or more strokes.

Abstract: A circuit component for use with signals of superhigh frequency, on the order of 10 GHz or more, has a waveguide structure with four conductive walls defining a channel of rectangular cross-section, the channel bottom being overlain by a dielectric layer supporting at least one microstrip of copper or the like closely spaced from one of the lateral walls. The supporting layer preferably consists of a polymeric material of relatively low dielectric constant, e.g. between 2 and 3. The width and height of the channel are less than half the free-space wavelength of the highest-frequency signal to be transmitted; the circuit is tuned by metallic screws which are threaded into the adjoining wall and partly overlie the microstrip at a low level, the axes of adjacent screws being separated by less than an eighth of that wavelength.

Abstract: A line loop (a, b) serving two telephone subscribers with sets (U.sub.1, U.sub.2) each normally connected between ground and a respective line conductor, coupled at the exchange via a line transformer (T) to a voice path, includes a pair of line relays (RA, RB) respectively inserted in these conductors in series with two high-ohmic resistors (RR.sub.1 ', RR.sub.1 ") and two low-ohmic resistors (RR.sub.2 ', RR.sub.2 ") forming part of a switching network (CI) which interfaces the loop with call-control circuitry (CCT) at the exchange. Two selection relays (RE.sub.1, RE.sub.2) in the switching network normally connect the two line conductors to negative battery whereby an off-hook condition at one set, grounding the corresponding conductor, causes a current flow insufficient to operate the associated line relay but detectable by a line monitor (RI.sub.1, RI.sub.2) connected across the low-ohmic resistor thereof which generates an engagement signal (i.sub.1, i.sub.

Abstract: A transmitting section of a PCM station in a telecommunication system, embodied in an integrated-circuit chip, comprises a channel-forming circuit receiving a stream of data bits to be organized into a succession of outgoing frames each consisting of a series of channels containing respective 8-bit words or bytes. A multiplexer in the channel former replaces part of a received byte assigned to the No. 0 channel of each frame, including its second and third bits, with certain bits to be included in two alignment words A and B respectively transmitted to a remote terminal at the beginning of alternate frames. The third bit of word B is high when a malfunction is detected or when the replaced second and third bits of the corresponding byte have certain configurations detected by a decoder, calling either for the closure of a loop between the local transmitting and receiving sections or for the monitoring of the PCM line extending to the remote terminal.

Abstract: Incoming data words organized in a succession of multi-channel frames, arriving at a receiving section of a PCM station, are fed in parallel therewith to a correlation circuit forming part of a synchronizing unit which includes a timer stepped by line-clock pulses extracted from the incoming bit stream. The correlation circuit includes a decoder which recognizes predetermined bits or bit combinations in alignment words A and B respectively appearing at the beginning of alternate frames. Recurrent noncoincidences of either of these alignment words with a corresponding marking pulse emitted by the timer, in a time slot designating the No. 0 channel of a frame, causes a readjustment of the timer and thus a shifting of clock signals emitted thereby to the receiving section. The synchronizing unit, embodied in an integrated-circuit chip, further includes a malfunction detector responsive to signals emitted by the timer and by the decoder of the correlation circuit.

Abstract: A tone generator for a telecommunication--especially telephone--system operating in the PAM/TDM mode comprises two complementary transistors with interconnected emitters joined to a "hot" conductor of a two-wire transmission path forming part of a trunk line between two groups of subscribers, the collectors of these transistors being connected through respective series resistors to a positive and a negative terminal of a DC source. These collectors are further coupled via respective shunt condensers to the "cold" conductor of the transmission path which is grounded through a low-ohmic further resistor.

Abstract: Two microwave signals of identical frequency, possibly differing in amplitude and/or phase from each other, are combined by feeding them to respective inputs of a directional coupler with outputs each carrying an unshifted component of one and a quadrature-shifted component of the other input signal. The composite output signals of the coupler are fed to a hybrid junction which combines them cophasally into a sum signal and with relative phase inversion into a difference signal. The sum signal, besides energizing a load, is applied directly to a reference input of a first coherent detector and through a 90.degree. phase shifter to a reference input of a second coherent detector each receiving the difference signal on a monitoring input. The first detector controls a phase shifter upstream of one of the coupler inputs to correct for phase deviations while the second detector controls a phase shifter downstream of one of the coupler outputs to correct for changes in relative amplitude.

Abstract: A printed-circuit board designed to energize a multiplicity of integrated chips or other modular units comprises on a first face two closely spaced main conductor strips, respectively connected to an ungrounded and a grounded terminal of a d-c source, extending along an edge thereof, together with a number of ancillary ground conductors paralleling these strips at substantially equispaced locations. The second face carries a multiplicity of branch lines perpendicular to the strips, each line consisting of two closely spaced leads respectively joined to the ungrounded strip and to the main and ancillary ground conductors through connectors traversing the board. The leads of each branch line are bridged by several storage capacitors and are so spaced apart and dimensioned as to provide a line inductance low enough to make the resonance frequency of the line substantially higher than the operating frequency of the associated loads.

Abstract: Two power transistors operating in push-pull, connected in series with respective halves of a transformer primary across a d-c source, are alternately rendered conductive by driving pulses generated during fractions of corresponding half-cycles of a square-wave oscillator. Two integrating networks, connected across these primary halves or across resistors in series therewith, work into a comparator whose output signal, reflecting a dissymmetry between the transistor currents, unbalances the square-wave oscillator to vary the relative width of the two sets of driving pulses until the dissymmetry substantially disappears.