Abstract: The present invention is a method for calibrating power spectral data obtained with an interferometer based Fourier transform spectrometer which utilizes a laser based coherent radiant source as the metrology source. A radiant beam of predetermined wavelength from a neon lamp based noncoherent radiant source is directed in parallel with a radiant beam from the laser source into the interferometer to create a laser based interference pattern and a neon lamp based interference pattern. Distinct fringe counts are derived from the laser based interference pattern and the neon lamp based interference pattern. The wavelength of the laser source is determined based on a correlation between the known wavelength of the neon lamp based interference pattern and the determined fringe counts. The scale of the power spectral data is calibrated based on the determined wavelength of the laser source.

Abstract: A microstrip line device is disclosed of the type which typically includes a strip conductor disposed on the top of a substrate. The device further includes a layer of dielectric material disposed between the strip conductor and the substrate for reducing the dissipation loss in these devices. In order to accomplish this, the dielectric layer has a dielectric constant which is less than the dielectric constant of the substrate.

Abstract: A monolithic integrable mixer network for a mixer console includes a variable gain preamplifier for each sound channel, a summing amplifier whose summing gain is adjustable differently for each sound channel, and a control unit which divides the channel gain for the respective sound channel between the preamplifier and the summing amplifier according to a ratio dependent on the desired channel gain to optimize the noise performance of the mixer network.

Abstract: A system is provided which includes a GPS receiver which determines its location as defined by three spatial coordinates and an associated time reference. The system includes a control logic unit which determines whether the location of GPS receiver is outside the permitted boundaries configured into an internal database in the system. The control logic unit is configured to transmit information related to the location of the GPS receiver to a remotely located interrogator apparatus which communicates back to the control logic unit, instructions regarding determination and reporting of the location of the GPS receiver. An interrogator, if included with a database, can be used as a shopping assistant to aid a shopper in locating desired items by polling a number of the GPS receiver, each associated with a different item, and informing the shopper of the floor, store, aisle or shelf where the item is located.

Abstract: A coupler device is disclosed which has an improved structure. The structure includes a substrate and, input ports and output ports disposed over the substrate. A plurality of inductors and capacitors are further included, which are arranged in a predetermined configuration and coupled between the ports. A layer of dielectric material is also disposed between the inductors and substrate which improves performance by reducing the dissipation losses and enhancing the frequency response of the coupler.

Abstract: An iterative interpolator permits linear interpolation between a first known value and second known value, which are defined by n-coordinate values in an n-dimensional coordinate system. An intermediate value to be interpolated is defined by n-1 intermediate values. By an interval nesting process in a first coordinate direction, an approximate value is formed for the first intermediate value. A copying device transfers this interval nesting process to the required coordinate value in the other coordinate direction.

Abstract: A complementary clock system is disclosed for producing antiphase clock signals. The system includes a clock generator for producing a first clock signal (t3) and a second clock signal (t4). A first and second driver stage coupled to the clock generator for driving respective clock lines having a capacitive load that corresponds to a first load capacitance and a second load capacitance, respectively. A switchable current path coupled between the first and second clock lines which contains a gating circuit and at least one inductive element. The gating circuit being in a conducting state essentially during the switching intervals (ti) of the first and second clock signals (t3, t4).

Abstract: An FET device is disclosed of the type typically fabricated on a substrate and including an active FET region, an input port, an output port, a common connection and via ground connections for coupling the common connection to a ground. The improvement includes the via connections being disposed on an outer periphery that bounds the active FET region which reduces the distance between the common connection and ground, and thereby reduces the associated common lead inductance.

Abstract: An improved method for digital interpolation of signals for a second interpolation filter is disclosed which permits a high signal/noise ratio with a minimum amount of circuitry for an overall system comprising first and second interpolation filters. The method for digital interpolation of signals requires multiplying delayed input values locked to a first signal by corresponding weighting factors which are dependent on a time-difference value determined by the interpolating instant and the time grid of the first clock signal. The weighting factors are determined by an impulse response in the time domain. The associated transfer function has an attenuation characteristic in the frequency domain which, with respect to the stop bands, is limited essentially to the alias regions located at the frequency multiples of the first clock signal.

Abstract: In an equalizer with n number of frequency ranges for digitized signals in which by means of n-1 cascaded filter circuits containing parallel connected digital low-pass filters and digital high pass filters whose respective frequency responses are linked by complementary transfer functions. A desired amplitude response is implemented via an increase or decrease in the amplitudes of adjacent frequency ranges in the associated filter circuit by weighting the outputs of the digital high-pass and low-pass filters, and a control unit forms the respective weighting factor from an equalizer control signal which contains the desired amplitude response as information.

Abstract: A photocathode device is disclosed including an active layer, a composition ramp layer and an emission layer including an emission surface. The active layer, ramp layer and emission layer each have both a predetermined material composition and a predetermined doping level for maintaining the conduction band of the device flat until the emission surface which functions to increase the photoresponse of the device.

Abstract: A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.

Abstract: A method is disclosed for limited write downs of data from higher security classification users to lower security classification users across computer networks, while preserving the security of classified data at the higher security classification user from covert transmission via acknowledgment messages from the higher user to the lower user. The intended acknowledgment message is released to the lower user when it matches the user content of a predicted acknowledgment message. In TCP/IP interface applications, the acknowledgment messages are IP based data transfer protocols acknowledging the transfer of data from the lower side to the higher side. With IP datagram transfers, deterministic portions are predicted and non-deterministic portions are identified. Where the number of non-deterministic bits exceed a predetermined rate, the acknowledgment message is discarded.

Abstract: A bus arbitration method for a multimaster system comprising a plurality of masters sharing a global data bus and a plurality of bus arbiters sharing a global identification bus. Each active bus arbiter applies to the identification bus a bus request signal containing a k-bit-wide identification word representative of the priority of the master associated with the bus arbiter. In each prioritization step of the bus grant cycle, a logic level is produced on the identification bus by logically combining bits of equal significance. This logic level is then compared with the corresponding bits of the applied identification words.

Abstract: A current mirror circuit including at least one current bank transistor coupled to a cascade transistor. The cascade transistor further coupled to a current mirror input. A current-controlled current source operable for both receiving a differential current from said current mirror input and for producing a charging current for charging a gate of the at least one current bank transistor in order to null the differential current.

Abstract: A programmable semiconductor memory is disclosed which can be fabricated with an MOS process of low complexity and which takes up little space. The memory comprises a MOS field-effect transistor having an antifuse region between the gate electrode and the drain region. Prior to application of a programming voltage, the antifuse region electrically isolates the gate electrode and the drain region from each other. On application of the programming voltage to the gate electrode, which is greater than the supply voltage applied between the drain and the source, the antifuse region changes to a low-impedance state.