Abstract: In a switching power converter, no-load condition is detected based on a variety of parameters including the output current, primary current, transformer reset time, and switching period. Once the no-load condition is detected, the switching power converter enters stand-by mode, in which the reference voltage corresponding to the target regulated output voltage of the switching power converter is lowered to a low stand-by value or the switching power converter is shut down for a predetermined duration. As a result, power loss during the stand-by mode of the switching power converter can be reduced significantly.

Abstract: A switch controller compensates the total on-time delay of the switch in a switching power converter. The intended on-time of the switching transistor for the present switching cycle is reduced by the time difference between the actual on-time and the intended on-time of the switching transistor in the previous switching cycle in the switching power converter. The total delay of the switch in the switching power converter, including propagation delay, switch turn-on delay, and switch turn-off delay, can be compensated in real time, cycle by cycle.

Abstract: An improved valley-mode switching (VMS) scheme and circuitry for implementing the improved VMS switching scheme in a switch-mode power converter are disclosed. For a given switching cycle, a desired switch turn-on time is determined based on a pulse width modulation, pulse frequency modulation, or other suitable power converter control scheme. Also, one or more times corresponding to local minimums (valleys) are predicted for the voltage across a power switch of the switching power converter. The power switch is turned on at a valley immediately subsequent or otherwise subsequent to the desired switch time determined according to the power converter control scheme. Thus, the improved VMS scheme enables low-voltage switch operation to reduce switching loss and EMI noise without restricting the control scheme of the power converter.

Abstract: Adaptive multi-mode digital control schemes that improve the light-load efficiency (and thus the overall average efficiency) in switch-mode power converters without causing performance issues such as audible noises or excessive voltage ripples. Embodiments include a switch-mode power converter that reduces current in the power converter using a second pulse-width-modulation (PWM) mode before reaching switching frequencies that generate audible noises. As the load across the output of the power converter is reduced, the power converter transitions from a first PWM mode in high load conditions to a first pulse-frequency-modulation (PFM) mode, then to a second PWM mode, and finally to a second PFM mode. During the second PFM mode, the switching frequency is dropped to audible frequency levels. Current in the power converter, however, is reduced in the second PWM mode before transitioning to the second PFM mode.

Abstract: A controller of an AC/DC flyback switching power supply uses adaptive digital control approaches to control the switching operation of a BJT power switch based on primary-side feedback to regulate the secondary-side constant output voltage and output current, without using the input line voltage. Switching-cycle by switching-cycle peak current control and limit are achieved based on the sensed primary-side current rather than the input line voltage in both constant-voltage and constant-current modes, operating in PWM, PFM and/or combinations of a plurality of PWM and PFM modes. The controller IC does not need a separate pin and ADC circuitry for sensing the input line voltage.

Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

Abstract: A switch controller compensates the total on-time delay of the switch in a switching power converter. The intended on-time of the switching transistor for the present switching cycle is reduced by the time difference between the actual on-time and the intended on-time of the switching transistor in the previous switching cycle in the switching power converter. The total delay of the switch in the switching power converter, including propagation delay, switch turn-on delay, and switch turn-off delay, can be compensated in real time, cycle by cycle.

Abstract: A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.

Abstract: An LED lamp is provided in which the output light intensity of the LEDs in the LED lamp is adjusted based on the input voltage to the LED lamp. The LED lamp comprises one or more LEDs, and an LED driver configured to receive an input voltage and provide regulated current to said one or more LEDs, where the LED driver is configured to adjust the regulated current to said one or more LEDs according to the input voltage to adjust the output light intensity of said one or more LEDs. The LED lamp can be a direct replacement of conventional incandescent lamps in typical wiring configurations found in residential and commercial building lighting applications that use conventional dimmer switches that carry out dimming by changing the input voltage to the LED lamp.

Abstract: An LED driver includes at least two interlocked closed feedback loops. One feedback loop controls the duty cycle of the on/off times of a switch connected in series to the LED string, and the other feedback loop controls the duty cycle of the on/off times of a power switch in the switching power converter that provides a DC voltage applied to the LED string. The LED driver of the present invention achieves fast control of the LED brightness and current sharing among multiple LED strings simultaneously in a power-efficient and cost-efficient manner.

Abstract: A power converter includes a switch controller having a dual output digital-to-analog converter for generating a variable reference voltage and a knee voltage offset from the reference voltage by a predetermined voltage. The variable reference voltage is generated based on a reconstructed representation of output voltage of the power converter in a previous switching cycle. Comparators compare the variable reference voltage and the variable knee voltage to a sensed output of the power converter in a first switching cycle. A digital logic of the switch controller receives signals from the comparators and determines a pulse signal for controlling an on-time and an off time of a switch in a second switching cycle.

Abstract: A power converter includes a switch controller generating a pulse signal controlling a switch to emulate peak current mode control. The switch controller generates a control voltage from a representation of an output voltage of the power converter and a reference voltage. Based on the control voltage and a representation of an input voltage of the power converter, the switch controller determines a peak current in that switching cycle. If the peak current detected exceeds a maximum peak current, an on-time of the pulse signal in the next switching cycle is decreased. The power converter also provides short circuit or overload protection by increasing an off-time of the pulse signal until the off-time exceeds a transformer reset time of a transformer. If the switch period increased to prevent short circuit or overload exceeds a limit, the pulse signal is shut off immediately.

Abstract: A power converter delivers electrical power from an electrical power source to a load according to a plurality of operation modes, where at least one of the operation modes is a peak current switching mode. Under the peak current switching mode, a switch controller controls the switch in the power converter to be kept on until the current through the switch reaches a peak current value corresponding to a given phase of the input voltage signal to the power converter. The peak current values have a reference shape, which may be a trapezoidal. The power converter may have any topology, such as a flyback-type power converter or a boost-type power converter.

Abstract: A power converter delivers electrical power from an electrical power source to a load according to a plurality of operation modes, where at least one of the operation modes is a peak current switching mode. Under the peak current switching mode, a switch controller controls the switch in the power converter to be kept on until the current through the switch reaches a peak current value corresponding to a given phase of the input voltage signal to the power converter. The peak current values have a reference shape, which may be a trapezoidal. The power converter may have any topology, such as a flyback-type power converter or a boost-type power converter.

Abstract: A method and apparatus to implement parallel current mode control that is suitable for digital and analog implementation. A duty cycle algorithm is composed of a voltage term and a parallel current term which depends on the inductor current change between the inductor current value at the beginning of a switching cycle and the reference inductor current value at the end of that switching cycle. Parallel current mode control can be applied to all DC-DC converters, including both non-isolated and isolated topologies. It can also be applied to AC-DC converters with power factor correction.

Abstract: A modification of a control loop of a primary side sensing power control system that uses a different and unique relationship to accomplish the constant current control while attenuating the affects of a ripple voltage.

Abstract: The present invention is a system and a method that controls the current limit such that it is maintained within a small range for any acceptable input voltages, e.g., 90 to 264 Volts RMS, causes the output voltage of a PWM controller to drop as the output load increases so as to maintain a constant current output, and does cycle by cycle calculation compensating for the VIN ripple output from the bridge and bulk filter capacitor so that no loop filter is required in the constant current mode.

Abstract: A voltage-to-current converter providing an output current with compensation for process-voltage-temperature (PVT) variations of a component in the voltage-to-current converter. The voltage-to-current converter includes a first voltage-to-current converter branch, a second voltage-to-current converter branch, and a compensation current path. The first voltage-to-current converter provides a first current to the output of the voltage-to-current converter based on a variable control voltage. The second voltage-to-current converter branch provides a second current based on a fixed voltage. The compensation current path provides a compensation current from the second voltage-to-current branch to the first voltage-to-current converter branch compensating variations in the first current caused by the PVT variations of the component in the first voltage-to-current converter branch.

Abstract: A primary side sensing power control system and method for constant current control that utilizes a relationship that involves the measured reset-time from the previous cycle to determine the primary side peak current and off-time for the next cycle. This control mechanism does not need the knowledge of input voltage or magnetizing inductance. Therefore, it removes the sensitivities of input voltage and magnetizing inductance to the output current limit. Furthermore, it uses a time measurement instead of a voltage measurement for the current calculation which in many cases is easier to perform.

Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.