Patents Assigned to IXYS Corporation
  • Patent number: 9948205
    Abstract: An AC line filter module includes AC-to-DC rectification circuitry. The rectification circuitry includes four low forward voltage rectifiers coupled together as two high-side rectifiers and two low-side rectifiers, where each low forward voltage rectifier includes an NPN bipolar transistor and a parallel-connected diode. A current splitting pair of inductors splits a return current so that a portion of the current is supplied to the collector of an NPN bipolar transistor that is on, and so that the remainder of the current is supplied to the base of the transistor that is on. Both low-side rectifiers are driven by these current splitting inductors. A pair of base current return diodes provides base current return paths. Due to the use of NPN bipolar transistors and no PNP bipolar transistors, manufacturing cost is reduced and efficiency is improved as compared to an implementation that uses low forward voltage rectifiers having PNP transistors.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 17, 2018
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9941256
    Abstract: A packaged inverse diode device exhibits superior commutation robustness. The device includes a stack of inverse diodes disposed within a housing. Each adjacent pair of inverse diodes is bonded together by an intervening DMB (Direct Metal Bonded) substrate structure. At one end of the stack of diode dice and DMB substrate structures is attached a first metal terminal. A second metal terminal is attached to the other end of the stack. The two terminals serve as package terminals of the overall device. In a novel method, the device undergoes severe commutation. A large forward current is made to flow through the diode stack, followed by a rapid reversal of the voltage across the stack to a large reverse polarity voltage. Despite a substantial rate of change of the commutation current at the onset of the reverse voltage condition, the inverse diode device is not damaged.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 10, 2018
    Assignee: IXYS Corporation
    Inventors: Frank Ettingshausen, Thomas Spann, Elmar Wisotzki
  • Patent number: 9935206
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 3, 2018
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 9929066
    Abstract: The baseplate of a power semiconductor device module makes reliable and superior thermal contact with a heatsink when fixed to the heatsink. The baseplate includes a rectangular plate portion, a first downward-extending peripheral heel extension portion, and a second downward-extending peripheral heel extension portion. In one example, the plate portion has four mounting holes for receiving mounting bolts. There is one mounting hole located adjacent each of four corners of the rectangular plate portion. The central portion of the bottom surface of the plate portion has a slightly convex downward shape. The strip-shaped first heel extension portion extends along a first edge of the bottom surface. The strip-shaped second heel extension portion extends along a second edge of the bottom surface opposite the first edge. Each of the first and second heel extension portions extends downward from the bottom surface for a distance of between thirty and five hundred microns.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 27, 2018
    Assignee: IXYS Corporation
    Inventor: Thomas Spann
  • Patent number: 9922864
    Abstract: A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N- type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 20, 2018
    Assignee: IXYS Corporation
    Inventors: Elmar Wisotzki, Christoph Koerber
  • Patent number: 9923324
    Abstract: An AC Line Filter/Rectifier Module (ACLF/RM) has a metal housing and an outward appearance of a conventional AC line filter, but the ACLF/RM includes circuitry that performs both EMI filtering and line filtering as well as very efficient AC-to-DC rectification. Rectification circuitry within the ACLF/RM rectifies an AC voltage signal received onto AC input module terminals and outputs a rectified version of the AC voltage signal onto DC output module terminals. The rectification circuitry includes at least one low forward voltage rectifier, where the low forward voltage rectifier includes a bipolar transistor and a diode. Inductive components perform both EMI filtering and line filtering as well as current splitting required to drive the bipolar transistors of the low forward voltage rectifiers. Due to the use of the low forward voltage rectifiers, the AC-to-DC conversion is more efficient than would be case were a conventional diode bridge rectifier employed.
    Type: Grant
    Filed: January 31, 2015
    Date of Patent: March 20, 2018
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9924573
    Abstract: A system for driving a multi-stage LED with low distortion and with current proportional to rectified input voltage is disclosed. In an exemplary embodiment, an apparatus includes LED groups connected in series to form an LED string having a first node, a last node, and intermediate nodes. The apparatus also includes current cells having inputs coupled to the nodes and outputs coupled to an output resistor. Each current cell selectively regulates current to flow between its respective input and the output resistor. The apparatus also includes a feedback circuit that generates a plurality of feedback voltages from a voltage level at the output resistor. When a selected current cell is enabled by a selected feedback voltage to regulate a selected current level from its respective input to the output resistor, upstream current cells are disabled by their respective feedback voltages.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 20, 2018
    Assignee: IXYS Corporation
    Inventors: Bret Ross Howe, Narasimham Patibandla
  • Patent number: 9911838
    Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 6, 2018
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9912331
    Abstract: A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 6, 2018
    Assignee: IXYS Corporation
    Inventor: Andreas Laschek-Enders
  • Patent number: 9857823
    Abstract: A programmable temperature compensated voltage reference is disclosed. In an exemplary embodiment, an apparatus includes a digital-to-analog converter (DAC) that uses a reference voltage and a code to generate a DAC output voltage. The apparatus also includes a temperature compensator that uses a temperature measurement (T) and the DAC code to generate a temperature compensation signal. The temperature compensation signal is represented by a third order polynomial equation. The apparatus also includes a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate a temperature compensated programmable reference voltage.
    Type: Grant
    Filed: March 26, 2016
    Date of Patent: January 2, 2018
    Assignee: IXYS Corporation
    Inventors: Eric Blom, Anatoliy Tsyrganovich, James Anderson
  • Patent number: 9842795
    Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: December 12, 2017
    Assignee: IXYS Corporation
    Inventors: Nathan Zommer, Kang Rim Choi
  • Patent number: 9837529
    Abstract: Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 5, 2017
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9813055
    Abstract: A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 7, 2017
    Assignee: IXYS Corporation
    Inventor: Andreas Laschek-Enders
  • Patent number: 9800159
    Abstract: A switching converter has a self-driven bipolar junction transistor (BJT) synchronous rectifier. The BJT rectifier includes a BJT and a parallel-connected diode, and has a low forward voltage drop. In a first portion of a switching cycle, a main switch is on and the BJT rectifier is off. Current flows from an input, through the main switch, through the first inductor, to an output. Current also flows through the main switch, through the second inductor, to the output. In a second portion of the cycle, the main switch is turned off but the inductor currents continue to flow. Current flows from a ground node, through the BJT rectifier, through the first inductor, to the output. The BJT is on due to the second inductor drawing a base current from the BJT. In one example, the main switch is a split-source NFET that conducts separate currents through the two inductors.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 24, 2017
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9793352
    Abstract: A combination switch includes an Insulated Gate Bipolar Transistor (IGBT), an anti-parallel diode, and a saturable inductor. The diode and inductor are coupled in series between a collector and an emitter of the IGBT. The inductor is fashioned so that it will come out of saturation when a forward bias current flow through the diode falls below a saturation current level. When the diode current falls (for example, due to another combination switch of a phase leg turning on), the diode current initially falls at a high rate until the inductor current drops to the saturation current level. Thereafter, the diode current falls at a lower rate. The lower rate allows the diode current to have a soft landing to zero current, thereby eliminating or reducing voltage and/or current spikes that would otherwise occur. Multiple methods of implementing and manufacturing the saturable inductor are disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: October 17, 2017
    Assignee: IXYS Corporation
    Inventors: Kyoung Wook Seok, Joseph James Roosma
  • Patent number: 9780202
    Abstract: A trench IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a novel waved contour so that it has thinner portions and thicker portions. When the IGBT is on, electrons flow from an N+ emitter, vertically through a channel along a trench sidewall, and to an N? type drift layer. Additional electrons flow through the channel but then pass under the trench, through the floating P well to the floating N+ well, and laterally through the floating N+ well. NPN transistors are located at thinner portions of the floating P type well. The NPN transistors inject electrons from the floating N+ type well down into the N? drift layer. The extra electron injection reduces VCE(SAT). The waved contour can be made without adding any masking step to an IGBT manufacturing process.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 3, 2017
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9780168
    Abstract: An IGBT includes a floating P well, and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a waved contour so that it has thinner portions and thicker portions. When the device is on, electrons flow laterally from an N+ emitter, and through a first channel region. Some electrons pass downward, but others pass laterally through the floating N+ well to a local bipolar transistor located at a thinner portion of the floating P type well. The transistor injects electrons down into the N? drift layer. Other electrons pass farther through the floating N+ well, through the second channel region, and to an electron injector portion of the N? drift layer. The extra electron injection afforded by the floating well structures reduces VCE(SAT). The waved contour is made without adding any masking step to the IGBT manufacturing process.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 3, 2017
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9780648
    Abstract: A sense resistor is placed in series with an output capacitor of a buck converter. The buck converter operates in a discontinuous mode such that there is a dead time in each switching cycle. A control circuit senses a voltage across the sense resistor and thereby generates a first signal ICS. The control circuit detects an offset voltage in ICS, where the offset voltage is the voltage of ICS during the dead time in a first switching cycle. The control circuit level shifts the entire ICS by the offset voltage, thereby generating a second signal ICLS. ICLS has the same waveform as the waveform of the inductor current. In a second cycle, ICLS is used to determine when to turn off the main switch and when the start of the dead time occurs. ICLS and the offset voltage are used together to determine when to turn the main switch on.
    Type: Grant
    Filed: August 30, 2014
    Date of Patent: October 3, 2017
    Assignee: IXYS Corporation
    Inventor: Anatoliy V. Tsyrganovich
  • Patent number: 9704832
    Abstract: A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 11, 2017
    Assignee: IXYS Corporation
    Inventors: Elmar Wisotzki, Frank Ettingshausen
  • Patent number: 9705417
    Abstract: A rectifier includes a larger Field Effect Transistor (FET1) and a smaller FET (FET2). A sense resistor is in series with FET2's body diode between a cathode terminal and an anode terminal. If the cathode terminal voltage is greater than the voltage on the anode terminal, then body diodes of FETs are reverse biased, the FETs are controlled to be off, and there is no current flow through the rectifier. If, however, the voltage on the anode terminal becomes positive with respect to the cathode terminal, then the body diode of FET2 starts to conduct and there is a voltage drop across the sense resistor. A comparator detects this condition and turns both FETs on. The rectifier is then conductive, so current can flow from the anode terminal, through the larger FET1, and to the cathode terminal, with a small forward voltage drop and without passing across the sense resistor.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 11, 2017
    Assignee: IXYS Corporation
    Inventors: Anatoliy V. Tsyrganovich, Leonid A. Neyman