Patents Assigned to IXYS, LLC
  • Patent number: 10050527
    Abstract: A sense resistor is placed in series with an output capacitor of a buck converter. The buck converter operates in a discontinuous mode such that there is a dead time in each switching cycle. A control circuit senses a voltage across the sense resistor and thereby generates a first signal ICS. The control circuit detects an offset voltage in ICS, where the offset voltage is the voltage of ICS during the dead time in a first switching cycle. The control circuit level shifts the entire ICS by the offset voltage, thereby generating a second signal ICLS. ICLS has the same waveform as the waveform of the inductor current. In a second cycle, ICLS is used to determine when to turn off the main switch and when the start of the dead time occurs. ICLS and the offset voltage are used together to determine when to turn the main switch on.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: August 14, 2018
    Assignee: IXYS, LLC
    Inventor: Anatoliy V. Tsyrganovich
  • Patent number: 10038383
    Abstract: A Low Forward Voltage Rectifier (LFVR) circuit includes a bipolar transistor, a parallel diode, and a capacitive current splitting network. The LFVR circuit, when it is performing a rectifying function, conducts the forward current from a first node to a second node provided that the voltage from the first node to the second node is adequately positive. The capacitive current splitting network causes a portion of the forward current to be a base current of the bipolar transistor, thereby biasing the transistor so that the forward current experiences a low forward voltage drop across the transistor. The LFVR circuit sees use in as a rectifier in many different types of switching power converters, including in flyback, Cuk, SEPIC, boost, buck-boost, PFC, half-bridge resonant, and full-bridge resonant converters. Due to the low forward voltage drop across the LFVR, converter efficiency is improved.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: July 31, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10038088
    Abstract: Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 31, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10014852
    Abstract: A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors coupled in series between a first terminal and a second terminal. The HVSTC also has a control terminal for turning on an off the power transistors of the stack. All of the power transistors of the stack turn on together, and turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage. Each power transistor, other than the one most directly coupled to the first terminal, has an associated bipolar transistor. In a static on state of the HVSTC, the bipolar transistors are off. The associated power transistors can therefore be turned on. In a static off state of the HVSTC, the bipolar transistors are conductive (in one example, in the reverse active mode) in such a way that they keep their associated power transistors off.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: July 3, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 10000423
    Abstract: Top and bottom metal plates of a DMB panel stack are simultaneously direct-bonded to the central ceramic sheet in a single high-temperature step. During this step, the DMB panel rests on an array of very small upwardly projecting ceramic contacts of a ceramic carrier. An amount of unoxidized carbon (e.g., a layer of graphite) is disposed on each contact projection such that an amount of carbon is disposed between the top of the contact projection and the metal oxide skin of the bottom metal plate. The carbon bonds with oxygen from the metal oxide skin, thereby preventing connection or direct-bonding of the ceramic contact projection to the second metal plate. This reduces imperfections in the metal of the bottom plate and reduces the amount of ceramic particles bonded to metal at contact sites. As a result, less post-bonding processing is required to make a high quality DMB substrate.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 19, 2018
    Assignee: IXYS, LLC
    Inventor: Thomas Spann
  • Patent number: 9992833
    Abstract: A system for driving a multi-stage LED with low distortion and with current proportional to rectified input voltage is disclosed. In an exemplary embodiment, an apparatus includes LED groups connected in series to form an LED string having a first node, a last node, and intermediate nodes. The apparatus also includes current cells having inputs coupled to the nodes and outputs coupled to an output resistor. Each current cell selectively regulates current to flow between its respective input and the output resistor. The apparatus also includes a feedback circuit that generates a plurality of feedback voltages from a voltage level at the output resistor. When a selected current cell is enabled by a selected feedback voltage to regulate a selected current level from its respective input to the output resistor, upstream current cells are disabled by their respective feedback voltages.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 5, 2018
    Assignee: IXYS, LLC
    Inventors: Bret Ross Howe, Narasimham Patibandla