Abstract: A system for programming a computer provides a set of software-based virtual machines each for instructing a computer to carry out a selected operation. Each virtual machine is represented by a virtual front panel displayed on a screen and each virtual front panel graphically displays operator controllable values of input and output parameters utilized by the virtual machine it represents. The system is adapted to synthesize a new virtual machine for instructing the computer to perform a sequence of operations wherein each operation is carried out by the computer according to the instructions of an operator selected one of the existing virtual machines. The system also creates a new virtual front panel for displaying input and output parameters associated with the new virtual machine. The system permits the operator to program the computer by directing synthesis of a hierarchy of virtual machines.

Abstract: A min/max time stamp for a multimeter provides display of minimum and maximum measured values recorded since enabling a min/max function. The minimum and maximum values, as well as a present value, may be displayed, together with the relative or absolute time at which the measured minimum or maximum occurred. An alert signal is generated to indicate a new maximum or a new minimum measurement.

Abstract: A coupling circuit for a multimeter adapted to perform multiple measurements includes a thermistor and constant current sources in series between an instrument input terminal and an instrument circuit adapted to source current for ohms measurements. Varistors shunt the constant current sources and are thermally coupled to the thermistor. An initial inrush of current is controlled by the constant current sources and when the voltage across a constant current source reaches the knee voltage of the paralleled varistor, the varistor shunts the constant current source and provides heat to the thermistor for insuring the latter will transition to its high resistance state. The thermistor then drops a substantial part of the input voltage, effectively disconnecting the low impedance ohms circuit from the input terminals and protecting the constant current source circuitry and varistors from extended application of high voltage.

Abstract: An improved open circuit detector for testing a thermocouple for an open circuit condition. The detector includes a generator for providing and sourcing a tone signal to the thermocouple, wherein the tone signal has a known frequency and amplitude. A monitor analyzes the amplitude of a particular frequency component of a tone signal across the thermocouple. If the amplitude of the particular frequency component exceeds a predetermined threshold, an output is provided for indicating an open circuit condition for the thermocouple.

Abstract: A dual time base, zero dead zone time domain reflectometer repetitively launches a predetermined number of stimulus pulses into a transmission system in synchronism with clock signals from a first time base, providing a measurement cycle. The duration of the launched stimulus pulses, determined by a predetermined number clock cycles from the first time base, exceeds the total propagation time of the system to be measured so that a time interval between a launch and a reflection may be measured within the launched pulse. A second time base, which has a predetermined period that differs from the period of the first time base and defines a measurement period divided into equal sub-periods, continuously produces clock signals, one or more of which may be counted during the time interval.

Abstract: A protective circuit for the input of a multimeter is provided with series connected thermistors partially shunted by a varistor whereby overload voltage is distributed between the thermistors enabling protection at higher voltage levels. Shunt connected varistors protect primarily against transient overloads and are thermally coupled to the aforementioned thermistors to bring the thermistors more rapidly to their high resistance condition such that damage to the varistors is avoided and continued protection is provided.

Abstract: A low power operational amplifier adjusts its output slew rate by providing additional bias current to its differential amplifier stage when the amplitude of the differential input signal exceeds a given threshold. The additional bias current provides an enhanced current for charging or discharging an internal compensating feedback capacitor of the operational amplifier. The power dissipation of the operational amplifier is kept low by employing FET transistors for the basic operational amplifier functions and by minimally biasing the slew rate enhancement circuitry associated with monitoring the amplitude of the differential input signal as well as providing the additional current to the differential amplifier stage when the amplitude of the differential input signal exceeds the given threshold.

Abstract: A high input impedance AC buffer for use in an instrument that does not require high frequency compensation or calibration. An op-amp receives an input signal that is to be measured via a high resistance input resistor and produces an output signal proportional to the input signal. A feedback resistor block and a feedback attenuator form the feedback path of the buffer and establish buffer gain. The low resistances of the feedback block and the feedback attenuator are substantially less than the resistance of the high resistance input resistor, precluding the need for compensation and calibration capacitors. A switching circuit operates to select resistors in the feedback resistance block and the feedback attenuator to provide predetermined gains for the buffer.

Abstract: A memory emulation test system is provided with a method of and system for fast functional testing of memories, such as boot ROMs, in microprocessor-based assemblies. The emulative test system includes a synchronization circuit which automatically re-arms itself and generates sync pulses on each and every UUT data access cycle to allow the UUT microprocessor to read every boot ROM memory location and collect data to be computed into a checksum or other signature to be compared with a predetermined signature representative of a correctly functioning and faultless boot ROM.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes many improvements and refinements which eliminate timing and non-linearity errors which accumulate due to a large number of switching operations that occur over an integrate cycle. The ADC includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to limit the voltage magnitude at the output of the integrator. Thereafter, during a de-integrate cycle, the input voltage is disconnected while progressively shallower ramps are measured with a high-speed clock for greater resolution and accuracy. The comparator has a slight hysteresis built in to slightly separate the switching thresholds for positive-going and negative going ramps.

Abstract: A token ring local area network (LAN) testing apparatus is provided. The apparatus is able to conduct a phase jitter measurement without disruption of normal token ring operation. The apparatus transmits a frame that includes phase jitter test data. This frame is transmitted into the token ring, together with a clock signal. After return of the frame with the phase jitter test data, a comparison is made between the recovered clock signal accompanying this frame and a reference clock signal. The result of this comparison provides a sample used in determining phase jitter. In making the measurement, an interpolation circuit is utilized to increase the resolution of the time difference between the recovered clock signal and the reference clock signal. A clamp circuit is used to ensure that each interpolation begins at the same reference voltage, as well as ensuring that the interpolation process is properly discontinued.

Abstract: A thermal power sensor for providing an output signal that is linearly related to the amount of power derived from a power source over a first range and that is square law related to the amount of power derived from a power source over a second range which may overlap the first range. The apparatus comprises a pair of matched transistors connected in a common emitter configuration. Each of the matched transistors is thermally coupled to a matched resistor so that heat generated in the resistor is transmitted to its respective transistor to cause temperature variations therein. The current through each transistor is a function of the temperature of the transistor. The matched transistors are connected in series with a pair of cascode transistors. The cascode transistors are connected to a first differential amplifier which senses and amplifies the differential voltage which results from any difference in current flow through the matched transistors.

Abstract: An instrument having a continuity test feature wherein a change in continuity state from open-to-short or short-to-open is captured and displayed. A comparator provides continuity state information for a circuit under test. A storage device receives the state information and provides logic indicative of the continuity state which is read by a controller that executes a continuity capture program initiated by keypad or function selector input. A first transition between different continuity states is captured during a present capture cycle and is displayed in a form indicative of the type of transition captured. Subsequent transitions during the present capture cycle are ignored.

Abstract: A multi-function, multi-mode switch for an instrument that changes the instrument between primary and secondary functions and between first and second modes of operation within the primary and secondary functions. The instrument changes from the first mode of operation to the second mode of operation when the switch is actuated for a first period of time. The instrument changes from the second mode of operation to the first mode of operation when the switch is activated for a second period of time. The instrument changes between the primary and secondary functions when the switch is operated for a third period of time. The switch controls a program that instructs the instrument to perform the appropriate operations. The program also instructs the instrument to confirm that an operation has occurred via audible and visual feedback.

Abstract: Method and apparatus for improving the signal-to-noise ratio of a divide-by-N phase-locked loop includes a variable divider circuit to provide a plurality of feedback signals of substantially equal phase. Each of the plurality of feedback signals includes a signal component and a noise component wherein the signal components of the plurality of feedback signals have substantially equal phase and wherein the noise components of the plurality of feedback signals are not substantially correlated. A respective plurality of control circuits is provided to combine the plurality of feedback signals with a reference signal to provide a plurality of control signals wherein each control signal is a substantially direct current voltage the magnitude of which is proportional to the phase difference between the reference signal and the feedback signal which comprised its origin.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.