Abstract: A signal whose RMS value is to be accurately determined is first converted into DC form by a relatively inaccurate RMS converter, such as a thermal RMS converter (15). The result is a first converter signal (Y.sub.1), which is stored for recirculation in a suitable storage device, such as a sample and hold circuit (17). Thereafter, the signal stored in the storage device is recirculated to the converter to create a second converter signal (Y.sub.2). Then, the second converter signal is subtracted from the doubled value of the first converter signal (2Y.sub.1 -Y.sub.2) to produce a corrected RMS signal (X). The difference between the first converter signal (Y.sub.1) and the corrected RMS signal (X) is then determined. This error signal (E) is stored. Next, a decision is made as to whether or not a fast mode of operation is to be followed. If it is not to be followed the corrected RMS signal is displayed.

Abstract: A programmable divide-by-N phase-locked loop having a pulse incrementor circuit and a single sideband mixer circuit embedded in the loop feedback path is disclosed. In each disclosed arrangement, one input port of the single sideband mixer receives the signals supplied by the phase-locked loop voltage controlled oscillator and, depending upon whether the mixer employed is configured for supplying an upper sideband signal or a lower sideband signal, either increases or decreases the frequency of the phase-locked loop feedback signal by a factor f.sub.s, where f.sub.s is the frequency of a control signal applied to the second input port of the signal sideband mixer. The pulse incrementor circuit receives the signal supplied by the single sideband mixer and, depending on whether the pulse incrementor is configured for deleting signal pulses or adding signal pulses, either decreases or increases the average frequency of the signals supplied to the phase-locked loop programmable divider by a factor f.sub.

Abstract: A universal circuit board probe assembly connects a variety of circuit board types to a diagnostic system. The probe assembly is an integrated system which includes a general purpose perforate platform having perforations in a uniform grid pattern, a plurality of floating connector pins of the type having an opposing double-action movement, a removable backing plate which confronts the platform, pin displacement modules which removably mount to the backing plate and are disposed to abut to the connector pins, means for aligning the backing plate with the platform and circuit board test points, means for urging the modules in contact with connector pins to activate the connector pins for testing, and means for causing the activated connector pins to engage test points on a circuit board to be tested.

Abstract: A process for producing thermally isolated semiconductor die and die produced by the process, plus improved apparatus using the die are disclosed. The process generally comprises the steps of: forming a desired semiconductor component or circuit in a semiconductor wafer (preferably a silicon wafer of <100> crystal orientation) having a protective layer (SiO.sub.

Abstract: A low phase noise signal source is disclosed which incorporates a voltage controlled oscillator (VCO) and a feedback network that, in effect, demodulates the VCO output signal and supplies negative feedback representative of the VCO signal noise to the VCO frequency control terminal. The feedback network includes a frequency discriminator of the type wherein a time delay network is connected to one input port of a phase detector, with the VCO output signal being supplied to the time delay network and the second input port of the phase detector. A variable phase shifter, responsive to the signal supplied by the phase detector, is included in one of the phase detector input paths to cause a zero crossover of the frequency discriminator transfer characteristic to occur at the frequency to which the VCO is tuned.

Abstract: A simulated ohms generating method and apparatus for calibrating electrical measuring instruments of the resistance and/or conductance measuring type are disclosed. First, the nature (current or voltage) of the internal power supply of the measuring instrument is determined by sequentially connecting two different resistors to the terminals of the instrument and determining if the current flow through the resistors changes (voltage source) or remains constant (current source). Depending upon the nature of the power supply one or the other of two sequences of steps are followed. While the sequences are somewhat different, they both include adjusting the output of a voltage source connected in series with a fixed resistor and applying the combination to the instrument to simulate a predetermined resistance (ohms) value. After this value is set, the instrument being calibrated is read to determine if the reading is the same as the predetermined resistance value being simulated.

Abstract: A programmable phase-locked loop frequency synthesizer having a feedback path that includes a tuned discriminator circuit is frequency modulated by coupling a portion of the modulating signal into the feedback path to effect modulation at rates which exceed the bandwidth of the phase-locked loop and by utilizing a portion of the modulating signal to frequency modulate the phase-locked loop reference signal to effect modulation at rates within the bandwidth of the phase-locked loop. A digitally controlled phase shifter that forms a portion of the discriminator tuning circuits in effect divides the phase-locked loop tuning range into a series of relatively narrow centiguous frequency bands. Data, representing deviations in the discriminator characteristics for each of these frequency bands, are stored in an erasable programmable read only memory.

Abstract: A phase-locked loop is disclosed that exhibits flat modulation characteristics over a wide range of carrier frequencies for either frequency or phase modulation at rates that are both within and outside the loop bandwidth. The disclosed arrangement is a programmable divide-by-N phase-locked loop frequency synthesizer wherein the feedback path includes a second phase-locked loop that serves as a tracking filter. Modulation is supplied to the main phase-locked loop via a first modulation path that couples the modulating signal to the frequency control terminal of the phase-locked loop voltage-controlled oscillator and via a second modulation path that couples the modulating signal to the phase-locked loop phase detector.

Abstract: A sample and hold (S/H) circuit that produces an output signal having essentially zero offset voltage error is disclosed. The S/H circuit includes a pair of operational amplifiers (OA3 and OA4) that are connected in circuit during both the sample and the hold modes of operation. In the sample mode of operation one of the operational amplifiers (OA3) receives the incoming signal through a first resistor (R1) and in accordance therewith controls the magnitude of an inverted voltage stored on a storage capacitor (C1); and, the other operational amplifier (OA4) senses the stored inverted voltage and, in accordance therewith, applies a feedback voltage to the signal input of OA3 through a second resistor (R2). In the hold mode of operation OA4 senses the voltage stored on C1 and, in accordance therewith, via R2 and OA3 controls the output voltage, which has the correct polarity due to the inverted voltage being inverted by OA3.

Abstract: A waveform digitizer particularly suitable for use in electronic test systems for analyzing and displaying analog signals is disclosed. A digitally derived reference voltage is compared with the analog signal to be digitized during a series of comparison sequences. Simultaneously with the start of each comparison sequence a digital clock is started. Each time the analog signal rises above, or drops below, the reference voltage a decision change detector produces an enable pulse. Each time an enable pulse occurs, a data word, having a portion related to the value of the digitally derived reference voltage and a portion related to the digital clock value, is stored and/or used to control a display. At the end of the first comparison sequence (determined when the digital clock value reaches a predetermined level) the reference voltage is incremented and a second comparison sequence started. These steps are repeated until the reference voltage reaches a predetermined level.

Abstract: An electrical contact assembly for electrically coupling a first contact location on a first side of a planar test fixture to a second contact location on the opposing side of the test fixture. A first tubular barrel is provided for fixably mounting through a test fixture. A second tubular barrel is mounted within said first barrel with one end disposed to extend toward said first contact location. The second tubular barrel is reciprocally movable within the first barrel between a first position extending toward said first contact location and a second position extending toward said second contact location. The second barrel is biased toward said first position. A plunger is mounted within said second tubular barrel with one end disposed to extend toward said second contact location. The plunger is reciprocally movable within said second barrel between a first position extending toward said second contact location and a second position extending toward said first contact location.

Abstract: An operational amplifier (33) is continuously switched back-and-forth between an auto-zero mode of operation and an accurate amplification mode of operation. During the auto-zero mode of operation, the junction between an offset voltage compensation (e.g., auto-zero) capacitor (35) and the noninverting input of the operational amplifier (33) is referenced to the input signal voltage via a bootstrap amplifier (31), rather than being tied to ground. Further, during the auto-zero mode of operation, the other end of the auto-zero capacitor (35) is referenced to the output of the operational amplifier (33), which is also connected to the inverting input of the operational amplifier. As a result, the auto-zero capacitor (35) is charged to a voltage level equal to the input offset voltage of the operational amplifier, but in polarity opposition thereto.

Abstract: A signal whose RMS value is to be accurately determined is first converted into DC form by a relatively inaccurate RMS converter, such as a thermal RMS converter (15). The result is a first converter signal (Y.sub.1), which is stored for recirculation in a suitable device, such as a sample and hold circuit (17). The first converter signal is also doubled (2Y.sub.1) and stored (41). Thereafter the first converter signal stored in the storage device is recirculated to the converter to create a second converter signal (Y.sub.2). Then, the second converter signal is subtracted (43) from the doubled first converter (2Y.sub.1 -Y.sub.2) to produce a highly accurate RMS output signal.

Abstract: Method and apparatus for comparison-type testing of electronic devices which generate analog waveform output signals. A reference unit output signal and an output signal of a unit under test are paired and selectively and synchronously compared in response to a common input signal. The comparison is performed by means of subtraction producing an error signal, which error signal is compared against a limit window. The limit window may have fixed or preferably programmable amplitude limits whereby a digital decision signal is generated whenever the limits are exceeded.

Abstract: A process for producing thermally isolated monolithic semiconductor die and die produced by the process, plus improved apparatus using the die are disclosed. The process generally comprises the steps of: forming a desired semiconductor component or circuit in a semiconductor wafer (preferably a silicon wafer of <100> crystal orientation) having a protective layer (SiO.sub.

Abstract: Determining the value of resistance directly, but inversely, based on conductance measurements, rather than directly, based on resistance measurements, is disclosed. A voltage drop of one polarity across a referenced resistance controls the charge rate of the capacitor of an integrator of a dual slope analog-to-digital converter for a known period of time. Thereafter the capacitor is discharged to a predetermined level (e.g., zero) for a measured period of time at a rate determined by a voltage drop of opposite polarity across an unknown resistance. The measured period of time is directly related to the conductance value of the unknown resistance and inversely related to the resistance value. The time measurement is stored in latches, which control a digital display.

Abstract: An apparatus and method for identifying faults in a digital logic circuit system combines the output of a feedback signature generator and a synchronous transition counter to provide a unique signature sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals of the circuit system produced in response to a preselected input signal pattern is processed synchronously through a feedback signature generator or feedback shift register network, such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network. A preselected portion of the output of the bit transition counting network is combined with a preselected portion of the bits of the shift register network to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system under test. The fault detecting capability approaches 100 percent with an imbedded indication of the input test pattern duration as verification.

Abstract: A converter that provides an analog (voltage) output signal that denotes either the period of an unknown low frequency signal or the ratio between the periods of two unknown low frequency signals is disclosed. The converter includes a ramp generator having a capacitor that is alternately charged in accordance with the periods of two low frequency signals. Between charging cycles the capacitor is discharged. When the period of an unknown low frequency signal is to be converted to analog form, one of the charge controlling signals is the unknown signal and the other signal is a known low frequency signal. When the ratio of the periods of two unknown low frequency signals is to be converted to analog form, the two unknown signals control the charging of the capacitor of the ramp generator.

Abstract: A frequency synthesizer utilizing a series of individual frequency generating circuits, each circuit containing two phase locked loops, the operation of the loops being under the control of a computer which translates the value of the desired frequency into specific digital commands for the individual circuits. In conjunction with this series of frequency generating circuits is a divider network to which the output of the last frequency generating circuit is applied. The divider network utilizes the generated range of frequencies either directly, routing them to the output, or divides the applied frequency, depending on the particular frequency to be supplied at the output.

Abstract: An amplifier circuit including provision for detecting non-linear circuit operation caused by the application of input signals that exceed either the amplifier dynamic range or the amplifier slewing capability is disclosed. The amplifier circuit includes the cascaded combination of a voltage amplifier stage, a voltage-to-current converter stage, a current limiter stage and an output stage. A first signal, obtained at the junction between a capacitor and resistor that are series connected between the signal common or ground potential and the input terminal to the output stage, is compared with a second signal obtained at the input terminal of the voltage to current converter stage. When the amplifier circuit is operating within the linear region these two signals are of equal magnitude or exhibit some other known relationship to one another.