Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
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Patent number: 7837196Abstract: There is provided a connection apparatus for connecting an image forming apparatus and a plurality of sheet post-processing apparatuses. This connection apparatus has a flapper portion for switching a plurality of conveying paths going toward the plurality of sheet post-processing apparatuses. Sensors are provided near inlet rollers and near output rollers, respectively. Outputs of the sensors are inputted to a wired OR circuit, so that an output of the wired OR circuit is supplied to a CPU of one of the connected sheet post-processing apparatuses.Type: GrantFiled: March 28, 2008Date of Patent: November 23, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki KaishaInventors: Ken Iguchi, Isao Yahata, Toshiaki Oshiro
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Patent number: 7839746Abstract: An optical disc apparatus includes: an obtaining unit obtaining a sensitivity coefficient indicating a relation between a light power of a semiconductor laser and a monitor value; a first deriving unit deriving a first monitor value in setting the light power at a peak power; a second deriving unit deriving a second monitor value in setting the light power at an erase power; a converting unit converting the first and the second monitor values into first and second light power values based on the sensitivity coefficient; a first calculating unit calculating a ratio between the first and the second light power values; a second calculating unit calculating a correction coefficient based on a setting value of a ratio between the peak power and the erase power and a calculation value of the ratio between the first and the second light power values; and a correcting unit correcting the light power of the semiconductor laser based on the correction coefficient.Type: GrantFiled: November 25, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Shigeru Shimakawa
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Patent number: 7839676Abstract: A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting.Type: GrantFiled: March 19, 2009Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kurose, Masanori Furuta, Tsutomu Sugawara
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Patent number: 7837191Abstract: A technique is provided that enables detection of the state of a sheet skew or the like without adding a special sensor or the like in a sheet carrying apparatus if possible. Information about sheet detection timing by two sensors that are arranged at different positions from each other in a sheet carrying direction and arranged at positions different from each other in a direction orthogonal to the sheet carrying direction is acquired. A skew of a carried sheet is determined in accordance with the acquired information.Type: GrantFiled: May 21, 2008Date of Patent: November 23, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki KaishaInventors: Hiroyo Katou, Yoshikatsu Kamisuwa
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Patent number: 7840408Abstract: The present invention provides a method and apparatus for training a duration prediction model, method and apparatus for duration prediction, method and apparatus for speech synthesis. Said method for training a duration prediction model, comprising: generating an initial duration prediction model with a plurality of attributes related to duration prediction and at least part of possible attribute combinations of said plurality of attributes, in which each of said plurality of attributes and said attribute combinations is included as an item; calculating importance of each said item in said duration prediction model; deleting the item having the lowest importance calculated; re-generating a duration prediction model with the remaining items; determining whether said re-generated duration prediction model is an optimal model; and repeating said step of calculating importance and the following steps, if said duration prediction model is determined as not optimal model.Type: GrantFiled: October 19, 2006Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Lifu Yi, Jie Hao
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Patent number: 7840181Abstract: A first bias circuit outputs a first direct-current voltage to charge a first capacitor based on a clock signal. A second bias that outputs a second direct-current voltage to charge a second capacitor based on a clock signal. A first MOS transistor has a gate and a source. The first direct-current voltage is applied between the gate and the source of the first MOS transistor to bias the gate of the first MOS transistor. A second MOS transistor has a gate and a source, and a drain connected to the source of the first MOS transistor. The second direct-current voltage is applied between the gate and the source of the second MOS transistor to bias the gate of the second MOS transistor. A coupling capacitor has a first end connected to the source of the first MOS transistor, and a second end to which an alternating-current signal is input.Type: GrantFiled: March 3, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Umeda, Shoji Ootaka
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Patent number: 7840960Abstract: A content distribution method distributes a package containing a content from a content distribution apparatus to a terminal of a content distribution destination and causes the terminal to expand and display the content contained in the distributed package by using expansion software provided in the terminal. Update data of the expansion software is inserted in the package in addition to the content. When the terminal cannot expand the content by using the expansion software provided in it, the terminal updates the expansion software provided in it by using the update data contained in the distributed package and expands the content by using the updated expansion software.Type: GrantFiled: May 27, 2005Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Akira Miura, Hiroshi Suu, Akihiro Kasahara, Kazunori Nakano
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Patent number: 7839172Abstract: A bidirectional buffer circuit includes a first terminal, a second terminal, a first output buffer to which a signal from the first terminal is input and which outputs the signal to the second terminal, a first one-shot buffer control circuit outputting a first control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, a first one-shot buffer temporarily driving the second terminal by the first control signal, a second output buffer to which a signal from the second terminal is input and which outputs the signal to the first terminal, a second one-shot buffer control circuit outputting a second control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, and a second one-shot buffer temporarily driving the first terminal by the second control signal.Type: GrantFiled: May 27, 2009Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Chikahiro Hori
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Patent number: 7838344Abstract: A method for manufacturing a semiconductor device includes steps of forming an embedded channel 12 in a semiconductor substrate 11, forming a resist layer on the embedded channel 12 through an oxide film 14, exposing the resist layer using a grating mask the light transmissivity of which varies toward transfer directions of electric charges, developing the exposed resist layer to form a resist mask having a gradient, forming a first impurity region 13 having a concentration gradient by injecting ions into the embedded channel 12 through the resist mask, and arranging transfer electrodes 15 at prescribed positions on the first impurity region 13 through the oxide film 14 after removing the resist mask, wherein a potential profile becomes deeper toward the transfer directions of the electric charges.Type: GrantFiled: January 13, 2009Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirokazu Sekine, Shu Sasaki
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Patent number: 7837625Abstract: In a tissue tracking imaging (TTI) method, a velocity distribution image from which a translation velocity component or a rotation velocity component resulting from movement of a body, etc. is removed is generated every time phase. By tracking a predetermined position of a tissue on the basis of the velocity distribution image and generating a motion information image, it is possible to provide a diagnostic image having higher reliability.Type: GrantFiled: October 20, 2004Date of Patent: November 23, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical System CorporationInventor: Yasuhiko Abe
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Patent number: 7838831Abstract: A substrate inspection method includes forming a conductive thin film on a surface of an inspection target substrate with a pattern formed thereon, generating an electron beam and irradiating the substrate having the thin film formed thereon with the electron beam, detecting at least any of secondary electrons, reflected electrons and backscattered electrons released from the surface of the substrate and outputting signals constituting an inspection image, and selecting at least any of a material, a film thickness and a configuration for the thin film, or at least any of a material, a film thickness and a configuration for the thin film and an irradiation condition with the electron beam according to an arbitrary inspection image characteristic so that an inspection image according to an inspection purpose can be obtained.Type: GrantFiled: March 21, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Ichirota Nagahama
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Patent number: 7839953Abstract: A transmission signal generating unit has a window function calculator that generates a window function that makes all frequencies without a center frequency of an input signal and its adjacent frequencies zero and makes the signal to noise ratio of the center frequency maximum; and a transmission signal generator that generates a transmission signal whose amplitude is modulated in a shape of an envelope curve based on the window function generated by the window function calculator.Type: GrantFiled: May 22, 2007Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuyoshi Shinonaga
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Patent number: 7838845Abstract: An ultraviolet irradiation water treatment apparatus includes a vessel having a cylindrical side portion, and plural rod-shaped ultraviolet lamps are disposed in parallel with a central axis of the side portion in the vessel. A water inlet pipe through which water flows into the vessel is provided in an outer wall of the side portion at a position in a tangential direction of an inner periphery of the side portion.Type: GrantFiled: April 21, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Norimitsu Abe, Takeshi Ide, Takahiro Soma, Seiichi Murayama, Masao Kaneko, Shojiro Tamaki, Masumi Nakadate, Akira Morikawa
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Patent number: 7839326Abstract: According to one embodiment, a portable terminal includes: a display unit that displays a present location of the portable terminal; a GPS receiver that calculates theoretical precision data determined theoretically by geometric arrangement of plural GPS satellites on the basis of location information of the GPS satellites, and performs a positioning process by which positioning data for indicating the present location of the portable terminal is calculated using arrival time of the radio wave; and a control unit that repeats the positioning process performed by the GPS receiver plural times to calculate a cumulative average of the positioning data, and calculates a difference between the cumulative average of the theoretical precision data and the cumulative average of the positioning data to display a cumulative average of the positioning data, when the difference equal to or less than a predetermined value successively continues predetermined number of times, as the present location of the portable terminaType: GrantFiled: June 23, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Wan Wang
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Patent number: 7839678Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.Type: GrantFiled: September 16, 2009Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Hitoshi Shiga
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Patent number: 7838990Abstract: A semiconductor package includes a base substrate on which semiconductor elements are disposed; a covering member which is provided to the base substrate, which covers the semiconductor elements, and which includes an opening at an end thereof at the side of the base substrate; and a connector substrate which is provided on the base substrate in a manner that the connector substrate closes the opening, which includes a first high-frequency signal line in an area located inside the covering member for a first surface, and which includes a second high-frequency signal line on a second surface being a surface on the opposite side of the first surface, the second high-frequency signal line being electrically connected to the first high-frequency signal line; wherein the base substrate is formed in a manner that the base substrate is located away from the second high-frequency signal line.Type: GrantFiled: January 13, 2009Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Fumio Yamamoto
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Patent number: 7839198Abstract: According to an aspect of the present invention, there is provided a semiconductor integrated device including: a level-shifting circuit including: a first and a second input nodes; and a first and a second output nodes; a first current mirror circuit connected with the first output node; a second current mirror circuit connected with the second output node; a first switch circuit series-connected with an input-side of first current mirror circuit; a second switch circuit series-connected with an input-side of the second current mirror circuit; a fifth switching element parallel-connected with the input-side of the first current mirror circuit; and a sixths switching element parallel-connected with the input-side of the second current mirror circuit.Type: GrantFiled: March 6, 2009Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Nakamura, Hideaki Ito
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Patent number: D627750Type: GrantFiled: June 15, 2010Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Suzuki
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Patent number: D627782Type: GrantFiled: February 9, 2010Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kentaro Ichise
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Patent number: RE41950Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink