Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
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Patent number: 7732990Abstract: A MEMS device includes: a first actuator having a first fixed end, including a stacked structure of a first lower electrode, a first piezoelectric film, and a first upper electrode, and being able to be operated by applying voltages to the first lower electrode and the first upper electrode; a second actuator having a second fixed end, being disposed in parallel with the first actuator, including a stacked structure of a second lower electrode, a second piezoelectric film, and a second upper electrode, and being able to be operated by applying voltages to the second lower electrode and the second upper electrode; and an electric circuit element having a first action part connected to the first actuator and a second action part connected to the second actuator.Type: GrantFiled: March 8, 2007Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Michihiko Nishigaki, Toshihiko Nagano, Takashi Miyazaki, Kazuhiko Itaya, Takashi Kawakubo
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Patent number: 7733516Abstract: In one embodiment of an image forming apparatus according to the invention, an overwrite data determination device for determining overwrite data so that a hard disk containing information on image forming jobs is overwritten with the overwrite data. An overwrite block size determination device for determining size of an equal-size block so that a disk memory area is divided into equal-size blocks to be overwritten with the overwrite data. The size of the equal-size block is larger than that of the overwrite data. Using the overwrite settings specified by the overwrite data determination device and the overwrite block-size determination device, a data erase control device overwrites the hard disk with meaningless data in order to erase data stored in the hard disk.Type: GrantFiled: January 13, 2006Date of Patent: June 8, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Kabushiki KaishaInventors: Masayasu Asano, Mitsuhiro Kinoshita
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Patent number: 7733694Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed on the first insulating film inside the trench; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a channel region formed between the source region and the drain region in the semiconductor substrate, a second insulating film formed on a surface of the semiconductor substrate; and a control gate electrode formed on the channel region and a surface of the second insulating film. The channel region is adjacent to the trench. A storage state of the nonvolatile semiconductor memory is formed by injecting or drawing charge into or from the floating gate electrode when a tunnel current flows through the first insulating film.Type: GrantFiled: August 11, 2006Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuya Matsuzawa
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Patent number: 7732077Abstract: According to one embodiment, a polymer electrolyte medium is represented by the following general formula (I) where R is sulfonic acid or phosphoric acid, and n is an integer from 1 to 8000.Type: GrantFiled: February 8, 2006Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Tomoaki Arimura
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Patent number: 7733717Abstract: A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay.Type: GrantFiled: July 31, 2008Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kono
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Patent number: 7734072Abstract: This is a system having a personal identification function to perform a registering operation not as an explicit one. The system simplifies the confirmation of an identification result thereby to improve dictionary updating conveniences. A device control apparatus is configured to include a face identification processor, a device setting unit and an interactive processor. The device control apparatus is configured to acquire personal data on the face image of a user, to identify a person matching the acquired personal data, by comparing the acquired personal data and registered personal dictionary data, to display the face image, as matching the identified person, at the registration time on the basis of the registered personal dictionary data, to receive such confirmation information from the user as to confirm whether or not the displayed person is identical to the user, and to set device environment parameters matching the confirmed person.Type: GrantFiled: February 28, 2006Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Osamu Yamaguchi
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Patent number: 7732908Abstract: A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.Type: GrantFiled: September 26, 2008Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Kiyokazu Okada
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Patent number: 7732925Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.Type: GrantFiled: February 11, 2005Date of Patent: June 8, 2010Assignees: SANYO Electric Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, NEC CorporationInventors: Yoshio Okayama, Akira Suzuki, Koujiro Kameyama, Mitsuo Umemoto, Kenji Takahashi, Hiroshi Terao, Masataka Hoshino
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Patent number: 7733730Abstract: A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor circuit forming a current mirror circuit, a resistive divider supplied with a negative voltage to be detected, and coupled to the end of the current path of the second MOS transistor circuit to generate a second voltage, a second voltage comparator circuit to compare the second voltage with a reference voltage and to generate a detection signal corresponding to the value of the negative voltage, and a detection circuit for detecting a temperature or power supply voltage, generate the control signal corresponding to the detection result, and supply the control signal to the first and second MOS transistor circuits.Type: GrantFiled: September 22, 2008Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Hashiba
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Patent number: 7733402Abstract: A solid-state image sensing device includes a pixel unit, analog-to-digital converter, controller, and adder. In the pixel unit, cells are two-dimensionally arranged on a semiconductor substrate. An output analog signal from the pixel unit is converted into a digital signal by the analog-to-digital converter and output. The controller controls the pixel unit and analog-to-digital converter, and causes the analog-to-digital converter to digitize a plurality of analog signals different in storage time in the pixel unit during the storage period of the electric charge of one frame. The adder adds digital signals corresponding to the analog signals different in storage time and output from the analog-to-digital converter.Type: GrantFiled: March 28, 2006Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshitaka Egawa, Shinji Ohsawa
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Patent number: 7733122Abstract: A first operation unit stores first code information having a bit length shorter than a first set bit, receives dictionary information expressing each set bit corresponding to each code information, reads the set bit corresponding to the first code information from the dictionary information to obtain the first set bit, and further, changes setting according to the first set bit to execute any of a plurality of operations so as to obtain an operation result. A second operation unit stores second code information having a bit length shorter than a second set bit, receives the dictionary information from the first operation unit, reads the set bit corresponding to the second code information from the dictionary information to obtain the second set bit, and further, changes setting according to the second set bit so as to execute any of the operations with respect to the operation result.Type: GrantFiled: February 11, 2009Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshikawa, Shigehiro Asano
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Patent number: 7731183Abstract: A paper feeding apparatus includes a cassette main body that stacks a paper therein, a sidewall that moves in a width direction of the cassette main body, an end wall that moves in a longitudinal direction of the cassette main body, a first movable member that is connected at one end to the sidewall and rotates around a shaft axially fixed to the cassette main body in connection with the sidewall, a second movable member that is connected at one end to the end wall and rotates around a shaft axially fixed to the cassette main body in connection with the end wall, a first detection unit that has a plurality of detection members and detects the size of the paper in the width direction, and a second detection unit that has a plurality of detection members and detects the size of the paper in the longitudinal direction.Type: GrantFiled: September 9, 2008Date of Patent: June 8, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Kabushiki KaishaInventors: Masahiro Ohno, Yousuke Ushiyama, Tokihiko Ise, Toshihiro Matsushima, Tetsuo Shiba
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Publication number: 20100132981Abstract: According to one embodiment, a printed wiring board includes an insulating layer, a first conductor pattern on the insulating layer configured to be a signal line, and a second conductor pattern on the insulating layer. The second conductor pattern includes a larger conductor area than the first conductor pattern, and a slit which allows the second conductor pattern to stretch to follow a thermal expansion of the insulating layer.Type: ApplicationFiled: October 15, 2009Publication date: June 3, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Kiyomi MURO, Gen FUKAYA
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Publication number: 20100133613Abstract: A semiconductor memory device includes a supporting substrate; an insulation film provided on the supporting substrate; a source layer provided on the insulation film; a drain layer provided on the insulation film; a body region provided between the source layer and the drain layer and being in an electrically floating state, the body region accumulating electric charges or discharging electric charges in order to store data; a boundary gate dielectric film provided at least on a boundary portion between the body region and the source layer and on a boundary portion between the body region and the drain layer; and a center gate dielectric film provided adjacently to the boundary gate dielectric film on the body region, the center gate dielectric film having more interface states than the boundary gate dielectric film has.Type: ApplicationFiled: September 22, 2009Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hironobu FURUHASHI
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Publication number: 20100138888Abstract: According to one embodiment, a receiver is connected via a communication network to a broadcast server that transmits a plurality of programs broadcast via the Internet. The receiver includes a storage module, a receiving module, a connection processor, a display module, and a determination module. The storage module stores channels of the programs. The receiving module receives input specifying a first program, from among the programs, to be viewed. The connection processor receives the first program or a second program that is automatically transmitted from the broadcast server from among the programs. The display module displays the first program or the second program. The determination module determines whether the display module displays the first program, and, when determining that the display module displays the first program, stores the channel of the first program in the storage module.Type: ApplicationFiled: July 6, 2009Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Kawada, Gen Omura
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Publication number: 20100137715Abstract: A scanning part ultrasonically scans a cross section of a subject corresponding to a frame period. The filter processor uses time-series received signals that are obtained from the scanning part corresponding to a plurality of frames to attenuate low-frequency components from the received signals of a plurality of locations within the cross section. The amplitude-comparator compares the amplitudes of the received signals with the amplitudes of the signals for which the low-frequency components have been attenuated, and the signals with smaller amplitudes are output. The image-generator generates morphological images of the subject based on the output signals from the amplitude-comparator.Type: ApplicationFiled: November 10, 2009Publication date: June 3, 2010Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEDICAL SYSTEMS CORPORATIONInventor: Akihiro KAKEE
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Publication number: 20100132991Abstract: According to one embodiment, an electronic device includes a housing, a printed circuit board, an electronic component, a bonding material, and chips. The printed circuit board is housed in the housing. The electronic component includes an electrode on a surface thereof that faces the printed circuit board. The bonding material is applied to at least part of the outer periphery of the electronic component on the printed circuit board to bond the electronic component to the printed circuit board. The chips are arranged at positions on the printed circuit board corresponding to the periphery of the surface of the electronic component to prevent the bonding material from intruding in a gap between the surface of the electronic component and the printed circuit board.Type: ApplicationFiled: September 1, 2009Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Minoru TAKIZAWA, Hidenori TANAKA
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Publication number: 20100134917Abstract: According to one embodiment, a disk drive capable of performing a dynamic offset control (DOC) is provided. The disk drive has an offset module and an updating module. The offset module calculates an offset value that changes during a one-rotation period of a disk, from the offset-measuring position data recorded in the disk. The updating module updates the offset value to a new one if a disk shift has occurred.Type: ApplicationFiled: April 9, 2009Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yuji SAKAI
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Publication number: 20100138591Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller stores management information of data stored in the second storing unit during a startup operation into the first storing unit and performs data management while updating the management information. The management information in a latest state stored into the first storing unit is also stored in the second storing unit. The management information includes a pre-log before and after change generated before a change occurs in the management information and a post-log, which is generated after the change occurs in the management information, concerning the change in the management information. The pre-log and the post-log are stored in the same areas of different blocks.Type: ApplicationFiled: February 10, 2009Publication date: June 3, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Toshikatsu Hida
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Publication number: 20100136904Abstract: According to one embodiment, an electronic device includes a communication module, an electrical field strength detector, a state detector, an output module, and an output controller. The communication module transmits and receives a radio signal. The electrical field strength detector detects electrical field strength of the radio signal transmitted and received by the communication module. The state detector detects a first state where the electrical field strength detected by the electrical field strength detector increases with the lapse of time and a second state where the electrical field strength detected by the electrical field strength detector decreases with the lapse of time. The output controller controls output from the output module based on the first state and the second state.Type: ApplicationFiled: September 8, 2009Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Gen WATANABE