Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
  • Patent number: 7197437
    Abstract: A Monte Carlo ion implantation simulation method includes finding a unit cell in which an implanted trial particle is present, finding a basic cell in which the trial particle is present among basic cells that form the unit cell, finding a directional range in which the trial particle travels, obtaining collision candidate atoms with their locations from a database according to the found basic cell and directional range, setting a thermal vibration displacement for each of the collision candidate atoms that has not set thermal vibration displacement, calculating a collision parameter and free-flight distance for each of the collision candidate atoms, selecting, as a collision atom, one of the collision candidate atoms that has a collision parameter smaller than a predetermined maximum collision parameter and a smallest positive free-flight distance, and calculating a collision between the trial particle and the collision atom to find the after-collision location and momentum of the trial particle.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takahisa Kanemura
  • Patent number: 7196932
    Abstract: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Takeuchi, Tomoharu Tanaka, Noboru Shibata
  • Patent number: 7197275
    Abstract: An image forming apparatus and image forming method including a low-noise mode at paper sheet reverse section to decrease a reverse convey speed of reverse conveyance by a reverse roller pair, where necessary, a reverse convey speed of reverse conveyance.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: March 27, 2007
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventor: Kazumasa Yasui
  • Patent number: 7197339
    Abstract: The present invention is a communication terminal apparatus capable of making communication with a base station connectable to a communication network.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Iimori
  • Patent number: 7196863
    Abstract: An actuator supports a head such that the head is movable in a radial direction of a disk. The actuator has a voice coil motor (VCM) used as a driving source for the actuator. A voice coil motor driver (VCM driver) supplies the VCM with a driving current for driving the VCM. During a head unload operation of using the actuator to retract the head to a ramp away from a recording surface of the disk, a driver driving unit drives the VCM driver by a voltage higher than that required for a non-head-unload operation.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuyuki Sakamoto
  • Patent number: 7197230
    Abstract: In order to search for an image recorded on an optical disk 10, a registration trigger is generated automatically or in response to an instruction of the user from a microcomputer block 30, a pointer indicating the recording position of a main image which is used as an index image in a preset area of the optical disk 10 via a data processor 36 and disk drive 32, index image data which becomes the index image is created in an encoder section 50 and data is recorded from an index image buffer memory 59 into a user menu file on the optical disk 10 via a formatter 56, data processor 36 and disk drive 32.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Hisatomi, Yuji Ito, Shinichi Kikuchi, Kazuhiko Taira, Hideo Ando
  • Patent number: 7196264
    Abstract: The present invention provides a dye sensitized solar cell comprising an n-type semiconductor electrode containing a dye, an opposed electrode, and a gel electrolyte arranged between the n-type semiconductor and the opposed electrode and containing a gelling agent and an electrolyte that contains iodine, wherein the gelling agent contains a compound including an N-containing group and at least one atomic group selected from a group consisting of a sulfonic group and a carboxylic group.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Murai, Satoshi Mikoshiba, Hiroyasu Sumino, Shuji Hayase
  • Patent number: 7197020
    Abstract: A radio communication system in which information of a unit length is constituted with a plurality of frames as a set and the information is transmitted/received between a base station and a mobile station. A control section of the base station decides, during a telephone communications, performed between the base station and the mobile station, when an instruction to switch the frequency to a second frequency is received from an upper order network via a transmission/reception section, a time interval for the telephone communication using the second frequency so as not to stride over a boundary of frame sets adjacent to each other.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naritoshi Saito
  • Patent number: 7195459
    Abstract: A Francis turbine with an improved shape of blades, which can reduce a circumferential velocity component generated in the flow downstream of the blades in a condition of a partial load operation, or reduce the secondary flow around the blades, is provided. A Francis turbine comprises a crown, a plurality of blades, and a band. The crown can rotate around a rotating axis. The blades are circumferentially arranged on the crown, each of which including an inner end as a trailing edge. The band is coaxially coupled with the crown by the blades. A distance Rc can be defined as a distance between the rotation axis and an end by the crown side of the trailing edge. A distance Rb can be defined as a distance between the rotation axis and an end by the band side of the trailing edge. The distance Rc and the distance Rb satisfy 0.2 ? R c R b ? 0.4 .
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Enomoto, Toshiaki Suzuki, Sadao Kurosawa, Takanori Nakamura
  • Patent number: 7196412
    Abstract: A multi-chip press-connected type semiconductor device comprises: a plurality of active element chips to control an electric current flowing in one direction; a plurality of diode chips that transmit the current in a direction opposite to the current transmitting direction of said active element chip; and electrode plates for said active element chip and for said diode chip, said electrode plates pressing from above and under with said plurality of active element chips and said plurality of diode chips being interposed therebetween; wherein said diode chips are disposed in all of outermost peripheral chip positions with no-existence of other chips adjacent to at least one side of a chip in a chip disposing region, and are disposed in internal layout positions surrounded with the outermost peripheral chip positions, and said diode chips to be disposed in the internal layout positions are arranged in order of a total number of other chips from the smallest that exist adjacently to at least one of a side and a v
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Hasegawa, Hideaki Kitazawa
  • Patent number: 7195531
    Abstract: An image display unit having a structure in which a heat-resisting fine particle layer is formed on a metal back layer disposed on a phosphor layer, and a getter layer is deposited/formed on the heat-resisting fine particle layer by vapor-depositing. The fine particle layer is desirably formed in a specified pattern, and a filmy getter layer is formed in a pattern complementary to the former pattern. The average particle size of heat-resisting fine particles which may use SiO2, TiO2, Al2O3, Fe2O3 is 5 nm to 30 ?m. Since abnormal discharging is restricted, the destruction and deterioration of an electron emitting element and a phosphor screen are prevented to provide a high-brightness, high-grade display.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Ito, Tsuyoshi Oyaizu, Takashi Nishimura, Satoshi Koide, Hitoshi Tabata
  • Patent number: 7196877
    Abstract: A magnetoresistive element includes a magnetoresistive film having a magnetization pinned layer, a magnetization free layer, and a nonmagnetic intermediate layer. A magnetization direction of the magnetization pinned layer is substantially fixed in an external magnetic field, a magnetization direction of the magnetization free layer is configured to change in the external magnetic field, and the nonmagnetic intermediate layer formed between the magnetization pinned layer and the magnetization free layer and has a stacked structure of a first non-metallic intermediate layer/a metal intermediate layer/a second non-metallic intermediate layer. The magnetoresistive element also includes a pair of electrodes coupled to the magnetoresistive film and is configured to provide a current in a direction substantially perpendicular to a surface of the magnetoresistive film.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Yoshikawa, Masayuki Takagishi, Tomomi Funayama, Kohichi Tateyama, Hitoshi Iwasaki, Hideaki Fukuzawa
  • Patent number: 7197574
    Abstract: A domain name system inquiry (DNS) apparatus and a domain name system inquiry method which are capable of obtaining a desired response at high speed even when there are a plurality of trees of domain name systems are provided. For this purpose, location information received by a current location information receiving device for receiving location information of the apparatus itself on a connected network is stored. Then, server information received by a server information receiving device for receiving server information about a DNS server to which an inquiry can be made is stored. Then, an inquiry request is transferred to at least one DNS server determined based on the location information and the server information, and based on a response therefor, the server information is rewritten, and a response result corresponding to the inquiry request is selected.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Ishiyama
  • Patent number: 7197272
    Abstract: There is disclosed an image reading process has determining an estimated size of an original based on a width of the original, securing a memory region, the memory region having capacity to hold a maximum image data associated with the estimated size, generating an image data as the original is conveying over the read window, loading the image data into the memory region, after the original passed the read window determining a page size based on the width and the image data.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: March 27, 2007
    Assignees: Kabushiki Kaisha Toshiba
    Inventor: Kazuhisa Suzuki
  • Patent number: 7195827
    Abstract: A perpendicular magnetic recording medium includes a substrate, an underlayer formed on the substrate, and containing at least one element selected from the group A consisting of Pt, Pd, Rh, Ag, Au, Ir and Fe, and at least one element or compound selected from the group B consisting of C, Ta, Mo, W, Nb, Zr, Hf, V, Mg, Al, Zn, Sn, In, Bi, Pb, Cd, SiO2, MgO, Al2O3, TaC, TiC, TaN, TiN, B2O3, ZrO2, In2O3 and SnO2, and a magnetic layer formed on the underlayer, containing at least one element selected from the group consisting of Fe, Co, and Ni, and at least one element selected from the group consisting of Pt, Pd, Au and Ir, and containing crystal grains having an L10 structure.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Maeda, Akira Kikitsu, Hiroyuki Hieda, Yoshiyuki Kamata
  • Patent number: 7196933
    Abstract: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Noboru Shibata
  • Patent number: 7196370
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type isolation region is formed between columns in the array of the NAND columns. The trench-type isolation region is formed in self-alignment with end portions of the channel region and a floating gate of the memory cell transistor, formed in self-alignment with the end portion of a channel region of the select transistor, and has a recess formed in at least the upper surface between the floating gates of the memory cell transistors.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Kai, Hiroaki Hazama, Hirohisa Iizuka
  • Patent number: 7196944
    Abstract: A voltage detection circuit control device includes a first voltage detection circuit which detects a first voltage, a second voltage detection circuit which detects a second voltage higher than the first voltage, and an operation signal generating circuit which is connected to the first and second voltage detection circuits and produces a signal for controlling an operation of the first voltage detection circuit on the basis of a voltage detection signal from the second voltage detection circuit.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keijiro Hijikata
  • Patent number: 7196311
    Abstract: A semiconductor photosensor comprises: a semiconductor substrate; a first photodiode formed on the semiconductor substrate; a second photodiode formed on the semiconductor substrate; a first amplifier circuit configured to amplify photocurrent from the first photodiode, the first amplifier circuit being formed on the semiconductor substrate; a second amplifier circuit configured to amplify photocurrent from the second photodiode, the second amplifier circuit being formed on the semiconductor substrate and having an amplifying characteristic substantially identical to that of the first photodiode; an infrared transmissive filter configured to attenuate visible light components relative to infrared light components in incident light, the infrared transmissive filter being provided on the second photodiode; and a subtraction circuit configured to output a difference between an output of the first amplifier circuit and an output of the second amplifier circuit, the subtraction circuit being formed on the semicond
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiko Takiba, Hiroshi Suzunaga
  • Patent number: 7196950
    Abstract: A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: March 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazushige Kanda, Hiroshi Nakamura