Abstract: Disclosed is image forming apparatus, including a photoconductor, a charger charging the surface of the photoconductor, a light source exposing the charged surface of the photoconductor to light to form a latent image, a developing unit supplying a liquid developing agent containing a liquid component and a solid component onto the photoconductor so as to convert the latent image into a visible image, a liquid component adjusting unit for adjusting the weight of the liquid component of the liquid developing agent on the surface of the photoconductor to meet the relationship of 0.1≦Ml/Ms≦4.0, where Ms represents the weight of the solid component of the developing agent supplied onto the photoconductor, and Ml represents the weight of the Liquid component of the developing agent, and a transfer unit transferring the visible image onto an image carrier.

Abstract: The CMP apparatus including a polishing pad having functional groups charged at an opposite polarity to that of the abrasives in the slurry, on its surface is used, so as to eliminate unnecessary Cu film (Cu wiring) and TaN film (barrier metal film) present outside the damascene wiring, by polishing.

Abstract: A data allocation control method is applicable to a data recording apparatus for writing and/or reading data to/from a recording surface of a disciform recording medium. In this method, data to be recorded on the recording surface is divided into a plurality of data blocks to be consecutively dealt with. Next, allocation information for designating each location of the plurality of data blocks is generated such that a second data block next to a first data block included in the plurality of data blocks is located to keep a predetermined interval from a location of the first data block.

Abstract: An upper electrode of an FRAM capacitor is connected to a diffusion layer on the surface of a semiconductor substrate via a contact hole, second interconnecting layer, contact hole, first interconnecting layer, and contact hole. The first interconnecting layer is formed at substantially the same level as the FRAM capacitor. This decreases the depth of the contact hole connecting the first interconnecting layer to the surface of the semiconductor substrate and thereby decreases the aspect ratio of this contact hole. This facilitates processing and filling this contact hole and allows micropatterning.

Abstract: A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a synchronous delay control circuit, a clock driver, an output control circuit, a delay monitor, and a control signal generator circuit. Accordingly, in a delay measuring mode, a delay in the input signal is set in the delay monitor based on a measurement start signal and a measurement stop signal. After completion of the delay measuring mode, the delay monitor causes the signal CLK, outputted from the clock receiver, to lag behind by a delay set in the delay measuring mode. Further, the delay monitor outputs the delayed signal to the synchronous delay control circuit.

Abstract: Of I, P, and B pictures contained in an MPEG 2 data stream, only the I picture is subjected to encryption such as scramble processing. Scramble rule data used at that time is stored in the lead-in area of an optical disk. A software DVD decoder reads the scramble rule data stored in the lead-in area, and its certification control module descrambles only the I picture. With this processing, the CPU power required for descramble processing can be reduced, and motion picture data can be decoded by the software DVD decoder in real time.

Abstract: Coding mode information, VBV buffer occupancy information, and display field phase information corresponding to a coded frame are extracted in units of coded frames of a video signal. Condition determination is performed, on the basis of these pieces of extracted information, with respect to a standardized editable point at which at least part of the coded data can be connected to another coded data seamlessly in terms of the coding mode, the buffer occupancy, and the display field phase. If it is determined that the editable point for which insertion designation is performed does not satisfy the standardized editable point conditions, the editable point, for which insertion designation is performed, is delayed until the conditions are satisfied, thereby inserting the editable point at the delayed time point.

Abstract: A three-dimensional image display apparatus of the invention can be easily operated by the operator while a three-dimensional image created by the apparatus is observed by him. A depth information maximum value acquisition circuit acquires depth information contained in a first image signal. A parallax control circuit controls the parallax amount of a second image signal on the basis of depth information contained in the first and second image signals such that an image corresponding to the second image signal can be three-dimensionally displayed in front of an image corresponding to the first image signal. A three-dimensional image synthesizer synthesizes the first and second image signals which has been controlled by the parallax control circuit, on the basis of the parallax amount of each image signal, such that images correspond to that the first and second image signals in the three-dimensional display space.

Abstract: A charged beam lithography system includes a charged particle gun for generating charged beams, a main deflecting system and a sub-deflecting system for deflecting the charged beams generated by the charged particle gun, and a control computer. The charged beam lithography system is designed to cause the surface of a substrate to be irradiated with the charged beams from the charged particle gun while continuously moving a stage, to write a desired pattern for each of stripes defined by the maximum deflection widths of the main deflecting system and the sub-deflecting system. The charged beam lithography system further comprises: a real time proximity effect correcting circuit for calculating an optimum dosage for each of the stripes by correcting the dosage of the electron beams in view of the influence of the proximity effect; and a cash memory for storing the optimum dosage data for at least two of the stripes.

Abstract: With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

Abstract: This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the same. A memory cell is constructed of capacitors formed in two end portions of an element formation region of a silicon substrate and a MOS transistor formed between these capacitors. The interval between gate electrodes of MOS transistors in adjacent memory cells is made larger than the intervals between these gate electrodes and gate electrodes formed outside the former gate electrodes. A portion above an n-type diffusion layer connected to a capacitor node is filled with a spacer insulating film, and an n-type diffusion layer connected to a bit line is covered with the spacer insulating film. A titanium silicide film is formed on one of these n-type diffusion layers and the gate electrodes.

Abstract: A color picture tube which prevents a change in convergence due to current leaked from a resistor during operation of the color picture, thus, providing a stable and satisfactory convergence characteristic in the overall region of the screen. The color picture tube comprises a main electron lens portion, a deflection yoke, and an inline electron gun that includes an electron beam generating portion for generating three electron beams in line consisting of a center beam and a pair of side beams. Distances between the center axis of the center beam passage hole and that of each of the side beam passage holes in a first electrode (G5), a second electrode (GM) and a third electrode (G6) are represented by Sg(1), Sg(2) and Sg(3). The first and second electrodes are separated by a gap L(1); and the second and third electrodes are separated by a gap L(2). The distance Sg(2) is set to satisfy the relationship: Sg(2)={L(1)×Sg(3)+L(2)×Sg(1)}/{L(1)+L(2)}.

Abstract: An adjustment method for active-matrix type liquid crystal display device adjusts the potential differences applied to liquid crystal layers in such a way that black images are displayed in one group of pixels with the same polarity of the potential difference during a single vertical scanning period while halftone images are displayed in another group of pixels with the same polarity of the potential difference during the single vertical scanning period.

Abstract: The rotation component supported rotatably with respect to the gantry includes a cylindrically-shaped rotation base, and a disk-like frame provided in parallel to the bottom surface of the cylinder of the rotation base so as to partition it at substantially a middle way through. The frame has a plurality of unit opening sections for arranging the unit, and further an opening section. The structural elements provided in the rotation component, namely, the X-ray tube unit, signal amplification unit, cooling unit, power units and power control unit are fit into the predetermined unit opening section of the frame, and are fixed onto the inner wall surface of the cylindrical rotation base.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: A semiconductor comprising a semiconductor device formed on a semiconductor substrate, an interlevel insulating film having holes and a ring-shaped groove in a circuit area formed on the semiconductor substrate and having the semiconductor element formed therein, the ring-shaped groove seamlessly surrounding an outer periphery of the circuit area, via plugs formed in the holes in the interlevel insulating film, a wiring connected to the plug electrodes and mainly comprising copper, and a via ring having a layer formed in the ring-shaped groove and mainly comprising aluminum, wherein no layer mainly comprising copper is formed in the via ring layer.

Abstract: A magnetoresistive element comprises an exchange coupling film having a under layer, an antiferromagnetic film and a ferromagnetic film, which are laminated in that order, the under layer including a metal having a face centered cubic crystal structure or hexagonal closest packing crystal structure which have a longer nearest neighbor atomic distance than that of the antiferromagnetic film. With this construction, it is possible to improve the exchange coupling field and to satisfy a stable output over a long period of time. A magnetoresistive element having a dual spin valve structure has a magnetization adjusting layer, which is antiferromagnetically connected to a pinned layer via an anti-parallel connection layer, to adjust the value of the product of the saturation magnetization of each of the magnetization adjusting layer and the pinned layer by the thickness thereof.

Abstract: An AC switch device of the present invention comprises an n− region formed on a p-type semiconductor substrate, first and second p-type regions separately formed in the n− region, a first source region (n+ region) and a first sense region (n+ region) separately formed in the first p-type region, a second source region (n+ region) and a second sense region (n+ region) separately formed in the second p-type region, first and second channel regions formed in upper parts of the first and second p-type regions located between the first source region (n+ region) and the first sense region (n+ region), on the one hand, and the second source region (n+ region) and the second sense region (n+ region), on the other, a first gate electrode formed above the first channel region with a gate insulating film interposed, and a second gate electrode formed above the second channel region with a gate insulating film interposed.

Abstract: An electrical circuit for measuring threshold voltages and also a circuit for controlling threshold value variations, while avoiding a need to significantly modify or alter the circuit layout, are provided. A semiconductor device has a plurality of substrate conductor regions commonly shared by multiple metal insulator semiconductor field effect transistors (MISFETs) of the same conductivity type, wherein each of the plurality of substrate conductor regions is electrically separated or isolated from one another.

Abstract: The present invention relates to a method of manufacturing a thin film transistor for use in a liquid crystal display apparatus or the like. In the method, impurity ions are implanted into a semiconductor by intermittently generating a plasma which generates impurity ions, for a predetermined period at a predetermined interval. By changing the duty rate at which the plasma is generated, the effective value of a beam current can be controlled over a wide range with excellent accuracy without changing rates of ions. As a result, it is possible to form a channel portion and a lightly doped drain layer of a field effect transistor which contains silicon as a main component, so that a field effect transistor and a liquid crystal display device can be manufactured with high quality and excellent productivity.