Abstract: Decoding apparatus comprises EX-OR circuit exclusive ORing the Reed-Muller code and exclusive Ored value of mask symbol candidate pattern and the information data corresponding to the pattern, first decoder calculating checksum of the EX-OR circuit output and majority-judging the checksum to decode a part of the second portion of the information data, second decoder exclusive ORing the EX-OR circuit output and a product of the part of the second portion and the orthogonal codes and majority-judging the exclusive OR result to decode a remaining part of the second portion, Reed-Muller encoder encoding the information data, and minimum detector detecting the minimum of Euclidean distance between an output from the Reed-Muller encoder and the Reed-Muller code supplied to the arithmetic operation unit while a plurality of candidate patterns of the mask symbols are supplied to the arithmetic operation unit.

Abstract: A method of forming a pattern comprising the steps of, forming a lower film on a substrate, the lower film being a film containing carbon atom at a ratio of 80 wt % or more, or a vapor phase deposition film, either applying an adhesion-promoting treatment to a surface of the lower film or forming an adhesion-promoting on the lower film, forming an intermediate film on a surface of the lower film, forming a resist film on the intermediate film, forming a resist pattern by conducting a patterning exposure of the resist film, forming an intermediate film pattern by transferring the resist pattern to the intermediate film, and forming a lower film pattern by transferring the intermediate film pattern to the lower film.

Abstract: Disclosed herein is a semiconductor device that comprises a semiconductor substrate and a semiconductor substrate and a wiring layer. The wiring is formed on the semiconductor substrate and has a first region and a second region. The first region comprises a conductive film and an insulating film formed by oxidizing a film of the same material as the conductive film and connected to the conductive film. The second region is provided on the first region and includes a wiring. The Gibbs free energy of the wiring decreases less than that of the conductive film when the wiring and conductive film are oxidized.

Abstract: An element isolation method of a semiconductor device comprises the steps of forming an oxide film on a semiconductor substrate; forming a nitride film on the oxide film; forming an isolation trench on the semiconductor device, the isolation trench being formed through the nitride film and oxide film; forming an oxide insulation layer on the semiconductor substrate to fill the isolation trench and cover the nitride film; flattening the surface of the semiconductor substrate to expose the nitride film by removing a surface portion of the oxide insulation layer in the isolation trench and the oxide insulation layer on the nitride film; heating the flattened semiconductor substrate in a nitrogen-containing gas atmosphere under reduced pressure to form an oxy-nitride film at an interface between an inside wall of the isolation trench and the oxide insulation layer in the isolation trench; and removing the nitride film and the oxide film on the semiconductor substrate.

Abstract: According to the present invention, there is provided a polishing method having the steps of forming a film to be polished, having a depressed portion and a protruding portion on a surface of a substrate, and polishing the film to be polished by relatively moving the substrate and a polishing table, while pressing the substrate having the film to be polished, onto a polishing cloth of the polishing table and supplying a polishing solution containing polishing grains, between the film to be polished and the polishing cloth, wherein an organic compound having a molecular weight of 100 or more, and containing at least one hydrophilic group selected from the group consisting of COOM1 (M represents an atom or a functional group which can form a salt when substituted with a hydrogen atom of a carboxyl group), SO3H (sulfo group) and SO3M2 (M2 represents an atom or a functional group which can form a salt when substituted with a hydrogen atom of a carboxyl group) is added to the polishing solution.

Abstract: Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.

Abstract: In a radio communication system formed by a plurality of radio base stations having respective service areas and a mobile radio terminal configured to transmit a data transmission request through one radio base station and receive requested data through at least one radio base stations, a radio control station is provided to predict a moving route of the mobile radio terminal according to a terminal location information obtained from the mobile radio terminal upon receiving the data transmission request from the mobile radio terminal through the one radio base station, select those radio base stations which have service areas containing at least a part of the predicted moving route, and deliver requested data to the selected radio base stations.

Abstract: A method of forming a copper oxide film comprises the step of forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film. A method of etching a copper film comprises the steps of forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method as recited in any one of claims 1 to 3, and removing the copper oxide film from the copper film using acid or alkali.

Abstract: In an interface security system between a plurality of devices mutually connected and transmitting/receiving a signal, the respective devices include respective selectors selecting a connection pattern between signals transmitted/received and external terminals for transmitting/receiving the signals and switching connections between the signals and the external terminals in accordance with a connection pattern selected, and the selectors of the respective devices select a connection pattern and switch the connections in synchronization between the respective devices.

Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on an interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.

Abstract: A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m<n. In addition, the AL circuitry is operable to perform multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry. The multiple parallel operations are performed responsive to a second single instruction decoded by the instruction decode circuitry.

Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.

Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.

Abstract: A non-volatile semiconductor memory device comprising a memory cell array having a plurality of electrically writable memory cells arranged in a matrix form, each of the memory cells having three or more logic states so as to store a multi-value data “i”(i=0, 1, . . . , n−1: n≧3), a plurality of data latch circuits for temporarily storing data controlling a write state of the plurality of memory cells of the memory array, write verify circuit for confirming the write state of the plurality of memory cells, and an “i” data batch verify circuit for batch-detecting whether or not the memory cell where data “i” in should be written reaches a memory state of data “i.

Abstract: A load detector for an elevator having a cage moving up and down in a shaft for transporting passengers and a cable hanging the cage, including a relative position detector configured to detect a relative position of the cage against the shaft; and a calculator configured to calculate a change of the relative position between the position of the cage just after landing at a floor and the position of the cage just before leaving the floor, and a load of the cage on the basis of the change of the relative position caused by an expansion and contraction of the cable.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A novel cathode ray tube apparatus is disclosed, in which a yoke portion with a deflection yoke mounted thereon has a basically rectangular non-circular section perpendicular to the tube axis. A separator of the deflection yoke has a section perpendicular to the tube axis expressed as (M+N)/(2*(M2+N2)½)<(SS+LS)/(2DS)≦0.90 where M:N is the aspect ratio, SS the outer diameter along the vertical axis, LS the outer diameter along the horizontal axis, and DS the maximum outer diameter.

Abstract: A MOSFET formed on an SOI substrate secures a high withstand voltage and a reduced element area. The SOI substrate includes an insulator layer and an n−-type semiconductor layer formed on the insulator layer. The MOSFET consists of a p-type impurity diffusion region formed on the semiconductor layer, an n+-type source region formed in a surface area in the p-type impurity diffusion region, a gate insulating layer formed on the p-type impurity diffusion region and covering a region between the source region and the semiconductor layer, a gate electrode formed on the gate insulating layer, an n+-type drain region formed on the semiconductor layer at a predetermined position separated from the p-type impurity diffusion region, and an n-type well formed around the drain region. The impurity concentration of the n-type well is lower than that of the drain region and higher than that of the semiconductor layer.

Abstract: A yoke portion with a deflection coil mounted thereon has a rectangular section perpendicular to the tube axis. A horizontal deflection coil of the deflection coil is formed of a loop winding including a pair of parallel portions extending along the both sides of the tube axis and crossover portions connecting the parallel portions. The crossover portion nearer to the neck is formed of a winding wound in the direction along the tube axis.