Patents Assigned to KABUSHIKI KAISHA TOSHIBA and
  • Patent number: 6070024
    Abstract: A copier includes a transfer charger for electrostatically transferring a toner image which is formed on a surface of a photoelectric drum to a sheet and a separation charger for separating the sheet with a toner image transferred thereto from the drum surface. A transfer guide is provided on a conveying path upstream of the transfer charger to guide the sheet toward a transfer point provided relative to the photosensitive drum. A separation supporter for supporting the sheet is provided above the separation charger.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Michiteru Oono
  • Patent number: 6068419
    Abstract: A base sheet path for peeled issue (29) for guiding a base sheet (7) in a direction different from a label issue port (22) after passing a peeling section (12) following the printing by a printing section (18) and a base sheet path for continuous issue (30) for guiding the base sheet to the label issue port (22) with labels (9) printed by the printing section (18) stuck on the base sheet are provided. Two operating modes, namely, the label peeled issue mode in which the base sheet is set to the base sheet path for peeled issue and the label continuous issue mode in which the base sheet is set to the base sheet path for continuous issue are executed selectively.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: May 30, 2000
    Assignee: Toshiba TEC Kabushiki Kaisha (Toshiba TEC Corporation)
    Inventors: Tsugio Shiozaki, Takeshi Tashiro
  • Patent number: 6070006
    Abstract: An object-oriented programming system which performs equivalent conversion on a class network structure.Program data including class data and relation data in entered from the class data input section (4) and the relation data input section (5). Program data is stored in the class data file (6) and relation data file (7). The range of equivalent conversion is entered from the conversion range input section (8), and an equivalent conversion mode is entered from the conversion mode input section (9). The equivalent conversion section (10) converts the program data based on the range and the mode. The output range of program data is entered from the display range input section (12), and the output format of program data is entered from the display format input section (13). The generation section (11) generates the display data of the program data in the diagram format. The display unit (2) displays the diagram of the display data.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Iriuchijima, Akihiro Yamashiro
  • Patent number: 6069396
    Abstract: The high breakdown voltage semiconductor device comprises an insulating film, a semi-insulating high resistance film formed on the insulating film, a first semiconductor layer of the first conductivity type formed on the high resistance film, a second semiconductor layer of the second conductivity type formed on a surface of the first semiconductor layer, a third semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer so as to be apart from the second semiconductor layer, and having an impurity concentration higher than that of the first semiconductor layer, and a resurf layer formed in a space between the second and third semiconductor layers on the surface of the first semiconductor layer, and having an impurity concentration lower than that of the second semiconductor layer.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideyuki Funaki
  • Patent number: 6069835
    Abstract: A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Matoba, Masaru Koyanagi
  • Patent number: 6070220
    Abstract: An interrupt program selection system which is provided with a central processing unit executing various types of control programs stored in a storage unit and which accepts an interrupt processing request from an external unit and selects from the storage unit an interrupt program corresponding to the accepted request comprises an interrupt request controller, a conversion table, and a jump code generating module. The interrupt request controller selects a highest-priority processing request from a plurality of interrupt processing requests. The conversion table contains start addresses of a plurality of interrupt programs corresponding to a plurality of interrupt processing requests. The jump code generating module generates a jump code which may be executed directly by the central processing unit as an instruction based on the start address of the interrupt program corresponding to the accepted interrupt processing request, and places the generated code in a memory space in the storage unit.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isao Katayama
  • Patent number: 6069371
    Abstract: A semiconductor rectifier in which the sum of loss during reverse recovery and loss in a conducting state can be suppressed even if the ratio between the periods of the conducting and blocking states varies and a method of driving the same are disclosed. A voltage is applied to a gate electrode formed in a face-to-face relationship with a base layer of a first conductivity type and an emitter layer of a second conductivity type with a gate insulation film interposed therebetween to form an inversion layer on the surface of the base layer of the first conductivity type. As a result, the base layer of the first conductivity type and the short layer of the first conductivity type are short-circuited to decrease the density of carriers in the base layer of the first conductivity type, loss during a reverse recovery operation can be suppressed.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Tomoki Inoue
  • Patent number: 6069402
    Abstract: A card having a smooth surface suitable for printing photographic images thereon, and a built-in electronic part, where the electronic part and an antenna are embedded in a first cured resin, and the top and bottom surfaces of the first cured resin are covered by a second cured resin. The first and second cured resins are applied to conform to the length and width of the card, and the surfaces of the second cured resin are further covered with a covering material.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Murohara
  • Patent number: 6069820
    Abstract: A discrete energy levels are introduced in a ferromagnetic layer of a magnetic device, and tunnel current flows through a plurality of tunnel junctions. The tunnel junctions are disposed between first and second electrodes and the first ferromagnetic layer is interposed between the two tunnel junctions. Variations of the tunnel current depend on the relationship between magnetization directions of the ferromagnetic layer and another ferromagnetic layer. Tunnel current varies between parallel relation and anti-parallel relation.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Inomata, Yoshiaki Saito, Tatsuya Kishi
  • Patent number: 6069083
    Abstract: Chemical mechanical polisher is disclosed. A polishing slurry stored in a polishing slurry tank, used in this polishing contains a solvent and polishing particles dispersed in the solvent. The polishing particles are selected from silicon nitride, silicon carbide, and graphite. The material to be polished is polished by using a polishing slurry containing silicon nitride particles until a silicon nitride etch stop layer is reached.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoto Miyashita, Masahiro Abe, Mariko Shimomura
  • Patent number: 6069828
    Abstract: An equalizing circuit is connected between a pair of bit lines. The equalizing circuit is made up of three MOS transistors and an equalization control signal is supplied to the gates of the MOS transistors. A sense amplifier circuit is connected to the bit lines. The sense amplifier circuit amplifies the potential difference occurring between the bit lines, for the detection of data. The equalization control signal is output from a level conversion circuit. An internal boosted voltage-generating circuit constantly generates a boosted voltage which is higher than an externally-applied power supply voltage applied to a power supply terminal. The boosted voltage is applied to the level conversion circuit. The level conversion circuit converts an input control signal, whose high-level voltage is equal to, or lower than the externally-applied power supply voltage, into the boosted voltage, thereby generating the equalization control signal.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kaneko, Takashi Ohsawa
  • Patent number: 6070053
    Abstract: In a radio communication system and radio communication apparatus, the ringing sound or melody of calling notification can be altered by users. A music data receiving section, a music data storage section and a music data reproducing section are provided within a controller. A calling party transmits a calling signal in which music data is appended to the message; a called party receives the calling signal through an antenna and radio section, where a music data receiving section is used to determine whether or not music data is contained in the received message in the calling signal, and, if it is contained, to perform ringing for calling notification with a speaker by using the music data.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomohisa Yamashita
  • Patent number: 6068595
    Abstract: By employing controlled setting of a phase-encoding direction in MRI, for imaging a tissue or blood flow composed of spins whose time T.sub.2 is rather short or ranges from 100 to 200 milliseconds, signal levels induced by the blood flow or the like are raised in order to maintain a good signal-to-noise ratio. An image enjoying an excellent depiction ability can be produced without the loss of information of directivities of blood flows or tissues running in diverse directions. An MRI system utilizing the Fourier transform comprises an element for scanning the same region to be imaged of a subject a plurality of times while changing phase-encoding directions, and an element for producing image data of one frame on the basis of MR rawdata of a plurality of frames.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsue Miyazaki, Nobuyasu Ichinose
  • Patent number: 6070180
    Abstract: A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit wiord length and the second arithmetic data string being composed of (m.times.n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Yusei Itaya, Masaru Ozeki
  • Patent number: 6069823
    Abstract: A non-volatile semiconductor memory device comprising a memory cell array having a plurality of electrically writable memory cells arranged in a matrix form, each of the memory cells having three or more logic states so as to store a multi-value data "i"(i=0, 1, . . . , n-1:n.gtoreq.3), a plurality of data latch circuits for temporarily storing data controlling a write state of the plurality of memory cells of the memory array, write verify circuit for confirming the write state of the plurality of memory cells, and an "i" data batch verify circuit for batch-detecting whether or not the memory cell where data "i" should be written reaches a memory state of data "i.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Takeuchi, Tomoharu Tanaka
  • Patent number: 6069437
    Abstract: A high thermal expansion member consisting of such as an Fe--Ni--Cr based alloy, a low thermal expansion member consisting of such as an Fe--Ni based alloy, and an intermediary member, which comprises one kind of metal selected from Fe, Al and Cu or an alloy comprising these metals, possesses a thermal expansion coefficient .alpha..sub.3 which is located between those of the high thermal expansion member (thermal expansion coefficient .alpha..sub.1) and the low thermal expansion member (thermal expansion coefficient .alpha..sub.2) (.alpha..sub.1 >.alpha..sub.3 >.alpha..sub.2), and is interposed therebetween, are laminated to form a thermal deformation member for an electron tube or a thermal deformation member for electric control. The intermediary member, without adversely affecting strength or long term reliability of the thermal deformation member, contributes to manufacturing cost reduction and improvement of workability.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiharu Matsuki, Satoru Habu, Hitoshi Nakajima
  • Patent number: 6069438
    Abstract: A color CRT including an envelope having a tube axis (Z) and including panel (21) having an inner surface on which a phosphor screen (23) is formed, a funnel (22) connected to the panel (21) and neck (25) connected to the funnel (22), an electron gun assembly (40) arranged in the neck (25) for emitting three in-line electron beams toward the phosphor screen (23), convergence magnetic structure (32) arranged outside of the neck (25) for generating a hexapole magnetic field in the neck (25), a first pair of magnetic members (33A, 33B) arranged outside of the neck on a horizontal axis faced to each other with the electron gun interposed therebetween and extending along the axis of the tube; and a second pair of magnetic members (60A, 60B) so arranged in the X-Y plane as to face each other on a Y-axis and elongated along the magnetic structure (32), respectively, the X-axis corresponding to the horizontal axis, the Y-axis corresponding to the vertical axis normal to the tube axis (Z).
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisakazu Okamoto
  • Patent number: 6070049
    Abstract: An image forming apparatus includes a developing device to form a developer image by developing an electrostatic latent image formed on an image carrier by developing using a developer, a transfer device to transfer a developer image formed on an image carrier, a fixing device to fix a developer image transferred on an image receiving medium, and a conveyor guide 7 arranged so that the image receiving medium with a developer image transferred thereon to guide from the transfer device toward the fixing device. The conveyor guide has contact portions made of a material that is charged to the same polarity as the developer on the image receiving medium as a result of the friction with the image receiving medium.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masatoshi Hayashida
  • Patent number: D425930
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Kurisu
  • Patent number: RE36721
    Abstract: A speech signal is input to an excitation signal generating section, a prediction filter and a prediction parameter calculator. The prediction parameter calculator calculates a predetermined number of prediction parameters (LPC parameter or reflection coefficient) by an autocorrelation method or covariance method, and supplies the acquired prediction parameters to a prediction parameter coder. The codes of the prediction parameters are sent to a decoder and a multiplexer. The decoder sends decoded values of the codes of the prediction parameters to the prediction filter and the excitation signal generating section. The prediction filter calculates a prediction residual signal, which is the difference between the input speech signal and the decoded prediction parameter, and sends it to the excitation signal generating section.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: May 30, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masami Akamine, Kimio Miseki