Abstract: An electrode arrangement of a vacuum circuit breaker for making and breaking electrical connection. The electrode arrangement has: a pair of contact members which are adopted for making contact to and release from each other by relatively moving to and from each other along a predetermined direction; a pair of electrically conductive bars being connected to the above pair of contact members, respectively, for providing electric conduction to the contact members; and a magnetizing device with a magnetic body for generating magnetic field parallel to the predetermined direction between the contact members. The magnetic body is composed of an iron alloy comprising 0.02 to 1.5% by weight of carbon and iron. The iron alloy may further contain at least one of manganese and silicon.

Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.

Abstract: A semiconductor integrated circuit device has a plurality of functional blocks. Each of the plurality of functional blocks comprises a DLL circuit for outputting a clock signal, at least one wiring portion for receiving the clock signal at one end thereof, and at least one load circuit for receiving the clock signal from the DLL circuit via the wiring portion. The DLL circuit receives a reference clock signal and a wiring portion and outputs the clock signal so that the phase difference between the reference clock signal and the second clock signal is a predetermined value. Thus, clock skew is reduced even if there is variation due to process.

Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.

Abstract: Respective unit displays forming a multiscreen display are divided into two halves: a front half cabinet containing a screen part, and a rear half cabinet containing a light box part. During use, rear half cabinet is fixed relative to a predetermined position in the front half cabinet. During shipping and storing, the rear half cabinet can be contained in the front half cabinet. Further, in fitting the screen, the screen is fixed as it is pressed against the fitting frame using wires, or the Fresnel lenses forming the screen are fitted to the fitting frames for the respective projecting units.

Abstract: The present invention is directed to a flash EEPROM in which a plurality of resist patterns are arranged like an island such that only an interlayer insulation film formed on a field oxide film is left in order to insulate drain diffusion layers of cell transistors in the row direction from each other when contacts of a memory cell group are subjected to PEP. Using the island-like resist patterns as masks, contact holes communicating with both the drain diffusion layers and source diffusion layers are made. Since, therefore, drain and source contact holes are arranged in matrix, the PEP margin can greatly be increased, thereby making it possible to prevent the problems of forming no contact holes and causing a short circuit between the gate and contact from arising.

Abstract: A phase detection circuit detects a phase of a phase detection signal output from a complex multiplication circuit. A frequency error detection circuit detects a frequency error of a phase-detected signal, with the first frequency error detection characteristic in which a first frequency domain is defined as a detection range. An average circuit converts a signal having the detected frequency error into a signal having a second frequency error detection characteristic in which a second frequency domain other than the first frequency domain is defined as a detection range. After the average circuit calculates an average of frequency error signals for each period of time, it converts an average signal into a signal having the original first frequency error detection characteristic and outputs it to an AFC loop filter.

Abstract: A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

Abstract: A master slave type flip-flop circuit having a master latch circuit ML and a slave latch circuit SL has a voltage level converter circuit 20 in the slave latch circuit SL to reduce the number of elements used in the circuit, which results in reducing the power consumption and in increasing the operation speed of the circuit.

Abstract: A fluid compressor comprises a sealing case, an oil reservoir formed to an inner bottom portion of the sealing case, in an installed state, for storing an lubricating oil and a compression mechanism having a helical blade structure housed in the sealing case. The compression mechanism comprises a cylinder, a rotating member arranged in the cylinder so as to perform eccentric motion and a helical blade interposed between the rotating member and the cylinder for defining a plurality of partitioned compression chambers. The fluid compressor further comprises an electric motor unit housed inside the sealing casing in operative connection to the compression mechanism. The compression mechanism has a vertical structure in which the fluid is compressed and transferred in a perpendicular direction in the installed state.

Abstract: A transmitter and a receiver for wavelength division multiplexing optical transmission need no multiplexer and can be made compact and manufactured easily while promising a high reliability of a system using them. By using second-order Bragg diffraction gratings to form the output mechanism, a plurality of DFB laser-type elements can be integrated so that their optical outputs adversely affect each other. Therefore, a plurality of lasers can be arranged coaxially to form a light source for wavelength division multiplexing optical transmission without using a multiplexer. By using the same mechanism on the part of a receiver, a demultiplexer can be omitted.

Abstract: An objective lens for focusing a laser beam onto an optical information medium is disclosed. The objective lens comprises a lens body and a flange portion arranged on the periphery of the lens body. The surface of the lens body facing the optical information medium is formed with a convex shape having a radius of curvature R as follows: 0.05 m<R<0.5 m. In this way, a dynamic pressure is generated due to the convex-shaped surface and the rotation of the optical disk. This generates a buoyancy which overcomes the maximum acceleration of the objective lens. In this manner, it becomes possible to avoid collision of the objective lens with the optical information medium even in the presence of relative tilts, such as tangential tilts, radial tilts, and shift tilts, between the optical information medium and the objective lens.

Abstract: A bit train of a plurality of continuous pixels is compressed according to a new run-length compression scheme. In this run-length compression scheme, the run information of one unit of compression includes run-length information indicating the continuous number of the same pixel data blocks, or the number of pixels followed, and pixel data having a two-bit configuration for discriminating three or more colors of the pixels.

Abstract: A scheme for realizing a high speed data transfer between memory spaces shared among computers in a distributed computer system, without requiring a complicated and inefficient communication protocol processing at the computer side. One region which is at least a part of a virtual memory space or a real memory space managed by one computer and another region which is at least a part of a virtual memory space or a real memory space managed by another computer are shared between these two computers, and a dedicated virtual connection is set up between these two shared regions. Then, a data transfer between these two shared regions is carried out by using the dedicated virtual connection. A virtual connection identifier of the dedicated virtual connection is registered into a corresponding page table entry in the page table, so that this virtual connection identifier can be obtained at a time of the data transfer by referring to the page table alone.

Abstract: In the image processing apparatus of the present invention, the dot pattern analysis section determines a plurality of black pixels neighboring a notice pixel of a predetermined positioned black pixel in a window of the binary image and determines a white pixel as a compensation pixel in the window in accordance with coordinates of the notice pixel and the plurality of black pixels. A notice pixel multivalued section converts the black pixel of the notice pixel to a multivalued half tone pixel and outputs the multivalued half tone pixel based on the coordinate of the notice pixel. A compensation pixel multivalued section converts the white pixel of the compensation pixel to a multivalued half tone pixel and outputs the multivalued half tone pixel based on the coordinate of the compensation pixel.

Abstract: To suppress the power-on current flowing when power is tuned on in the circuit which feeds precharging current to the bit lines of the banks in a synchronous DRAM comprising a multi-bank structure. The device comprises a plurality of bank circuits BKi which are all of the same structure, wherein the bit line precharging power supply lines which the respective bank circuits have are connected in common, a first precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation when the power supply in the DRAM chip is turned on, and a second precharging power supply circuit which has its output node connected to the precharging power supply line and starts its precharging current feed operation after the bit line has been raised to a predetermined potential by the precharging current of the first precharging power supply circuit.

Abstract: There is provided a reactor internal equipment hoisting apparatus which is hung down from an upper side of a reactor pressure vessel to hoist reactor internal equipment installed inside the reactor pressure vessel. The hoisting apparatus includes a supporting unit which is hung down from the upper side of the reactor pressure vessel with an overhead travailing crane installed on the ceiling of the reactor building, and an elevating unit which is arranged below the supporting unit. A coupling/fixing unit is provided to the elevating unit to be releasably coupled with a hoisting lug. Power hoist using a wire rope or a chain is provided to the supporting unit. The elevating unit is hung down from the supporting unit via the rope or the chain to be moved vertically. This reactor internal equipment hoisting apparatus is easy in maintenance and storage.