Patents Assigned to Kanto Sanyo Semiconductors Co., Ltd.
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Patent number: 7919875Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: GrantFiled: December 13, 2007Date of Patent: April 5, 2011Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
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Patent number: 7906430Abstract: A peeling prevention layer for preventing an insulation film and a protection layer from peeling is formed in corner portions of a semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.Type: GrantFiled: April 25, 2008Date of Patent: March 15, 2011Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
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Patent number: 7728438Abstract: An optical semiconductor device of which the moisture resistance and the like are improved and the manufacturing method thereof are provided. An optical semiconductor device of the embodiment is configured to include an optical semiconductor element on a surface of which a circuit portion including a light-receiving or light-emitting element is formed; a terminal portion which is provided on a back of the optical semiconductor element and electrically connected with the circuit portion; a covering layer which covers the surface of the optical semiconductor element and is made of a transparent material; and sealing resin which covers side faces of the covering layer and of the optical semiconductor element. The circuit portion and the terminal portion may be connected by a rewiring pattern.Type: GrantFiled: September 29, 2006Date of Patent: June 1, 2010Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Koujiro Kameyama, Kiyoshi Mita
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Patent number: 7670955Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.Type: GrantFiled: January 3, 2008Date of Patent: March 2, 2010Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
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Patent number: 7646100Abstract: The first pad electrode layer is disposed on the surface of the semiconductor substrate with the first insulating film between them. Then, the second insulating film with the first via hole partially exposing the first pad electrode layer is formed over the first pad electrode layer. The plug is formed in the first via hole in the next process. The second pad electrode layer connected to the plug is disposed on the second insulating film. Next, the second via hole reaching to the first pad electrode layer from the backside of the semiconductor substrate is formed. The penetrating electrode and the second wiring layer connected to the first pad electrode layer at the bottom part of the second via hole are disposed. Furthermore, the protecting layer and the conductive terminal are formed. Finally, the semiconductor substrate is diced into the semiconductor chips.Type: GrantFiled: October 28, 2005Date of Patent: January 12, 2010Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
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Patent number: 7605475Abstract: The invention reduces outside dimensions of a semiconductor device mounted with a semiconductor die on an external connection medium and minimizes degradation of electrical characteristics of the semiconductor device. The semiconductor device of the invention having a semiconductor die and a lead frame with a plurality of lead terminals has following features. The semiconductor die has a plurality of pad electrodes formed on its front surface, at least one via hole penetrating the semiconductor die, a columnar electrode electrically connected with the pad electrode through the via hole, and a protrusion electrode electrically connected with the columnar electrode. At least one of the lead terminals of the lead frame is formed extending to a position connectable with the protrusion electrode, being connected with the protrusion electrode.Type: GrantFiled: March 23, 2005Date of Patent: October 20, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventor: Isao Ochiai
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Patent number: 7582971Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A refractory metal layer is formed on a pad electrode formed on a semiconductor substrate with a first insulation film therebetween. Next, a passivation layer is formed on a front surface of the semiconductor substrate including on the pad electrode and on the refractory metal layer, and a supporting body is further formed with a resin layer therebetween. Next the semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to the pad electrode. Next, a penetrating electrode electrically connected with the pad electrode exposed at a bottom of the via hole and a wiring layer 21 are formed with a second insulation film therebetween. Furthermore, a solder resist layer and a conductive terminal are formed.Type: GrantFiled: October 25, 2005Date of Patent: September 1, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
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Patent number: 7566588Abstract: To provide a semiconductor device 10, which is thin, compact, and excellent in mechanical strength and humidity resistance. Semiconductor device 10A has a configuration such that in semiconductor device 10A, wherein an optical semiconductor element 14, having a light receiving part or a light emitting part, is sealed in a sealing resin 13, a cover layer 12, covering the top surface of optical semiconductor element 14, is exposed from the top surface of sealing resin 13. Thus in comparison to a related-art example with which the entirety is sealed by a transparent resin, sealing resin 13 can be formed thinly and the thickness of the entire device can be made thin. Furthermore, semiconductor device 10 is arranged using a sealing resin having a filler mixed in. A semiconductor device that is excellent in mechanical strength and humidity resistance can thus be arranged.Type: GrantFiled: October 13, 2006Date of Patent: July 28, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Koujiro Kameyama, Kiyoshi Mita
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Patent number: 7531785Abstract: In a circuit device having a circuit element housed in a case, a rise of air pressure and occurrence of condensation in the case are prevented. A circuit device of the present invention includes a case formed of a bottom part and a side part, and a cover part covering an upper surface of the side part. In an internal space of the case, a circuit element such as a semiconductor element is housed. In a bottom part of the case, a land and leads are buried. A communicating part which causes the internal space of the case to communicate with an outside of the case is provided in the land. By providing the communicating part, the rise of air pressure and occurrence of condensation in the internal space due to change in temperature are suppressed. Furthermore, in the land made of metal, the communicating part can be easily formed by etching or the like.Type: GrantFiled: June 23, 2006Date of Patent: May 12, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventor: Hiroshi Inoguchi
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Patent number: 7511320Abstract: The invention is directed to an improvement of reliability in a chip-size package type semiconductor device and a manufacturing method thereof. A semiconductor substrate formed with a pad electrode is prepared, and a first protection layer formed of epoxy resin is formed on a front surface of the semiconductor substrate. Then, a via hole is formed from a back surface of the semiconductor substrate to the pad electrode. A wiring layer is then formed from the via hole of the semiconductor substrate, being electrically connected with the pad electrode through the via hole. Then, a second protection layer and a conductive terminal are formed, and the semiconductor substrate is separated into individual semiconductor dies by dicing.Type: GrantFiled: April 22, 2005Date of Patent: March 31, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventor: Isao Ochiai
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Patent number: 7495881Abstract: The invention provides an electrostatically chucking technology capable of chucking a workpiece formed of an insulator or a workpiece attached with an object to be processed such as a semiconductor wafer on a stage. A layered body attached with a glass substrate for supporting a semiconductor substrate having an electronic device on its surface is prepared, and a conductive film is attached thereto. Then, the layered body is set on a surface of a stage set in a vacuum chamber such as a dry-etching apparatus. After then, a voltage is applied to an internal electrode to generate positive and negative electric charges on the surfaces of the conductive film and the stage, and the layered body is chucked with static electricity generated therebetween. Then, the layered body chucked on the stage is processed by etching, CVD, or PVD.Type: GrantFiled: November 28, 2005Date of Patent: February 24, 2009Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Kojiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto
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Patent number: 7456083Abstract: The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a manufacturing method of a semiconductor device where a semiconductor wafer attached with a glass substrate is cut with moving a rotation blade along a dicing region and has following features. A pair of alignment marks is formed facing each other over the dicing region on the semiconductor wafer. Then, when the rotation blade is to be aligned on a center of the dicing region, that is, on a centerline thereof in the cutting process, positions of the alignment marks are detected by a recognition camera, the centerline is calculated based on the detection result, and the rotation blade is aligned on the centerline to perform cutting.Type: GrantFiled: March 2, 2005Date of Patent: November 25, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventors: Takashi Noma, Yoshinori Seki, Motoaki Wakui
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Patent number: 7443043Abstract: A circuit device 10 comprises a die pad 11, bonding pads 12, a circuit element 9, affixed onto die pad 11, and an insulating resin 14, which seals die pad 11, bonding pads 12, and circuit element 9, and has a configuration wherein recessed parts 15 are formed at parts of the side surfaces of insulating resin 14, and side surface of the conductive patterns that are disposed at peripheral parts are exposed from recessed parts 15. By bonding pads 12, which are to become connecting electrodes to the exterior, being exposed at the side surfaces, fillets of a brazing material 19 are formed at the sides of the device when circuit device 10 is mounted.Type: GrantFiled: December 11, 2003Date of Patent: October 28, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventor: Noriaki Sakamoto
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Publication number: 20080254618Abstract: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.Type: ApplicationFiled: April 25, 2008Publication date: October 16, 2008Applicants: SANYO ELECTRIC CO., LTD., Kanto SANYO Semiconductors Co., Ltd.Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
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Patent number: 7432580Abstract: A semiconductor apparatus comprises a substrate, a semiconductor chip fixedly secured on one side of the substrate, a spirally shaped coil formed on the other side of the substrate and electrically connected to the semiconductor chip, and a conductive pattern formed on a surface of the one side of the substrate facing to the semiconductor chip for stabilizing an inductance characteristic of the coil.Type: GrantFiled: December 20, 2005Date of Patent: October 7, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Akihiro Sato, Satoru Sekiguchi, Kiyokazu Kamado, Kazunari Kurokawa, Makoto Tsubonoya, Kiyoshi Mita, Yoichi Nabeta, Tetsuro Sawai, Toshikazu Imaoka
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Patent number: 7397128Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: GrantFiled: March 28, 2006Date of Patent: July 8, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
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Publication number: 20080132038Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.Type: ApplicationFiled: January 3, 2008Publication date: June 5, 2008Applicants: SANYO ELECTRIC CO., LTD., KANTO SANYO SEMICONDUCTOR CO., LTD.Inventors: Kojiro Kameyama, Akira Suzuki, Mitsuo Umemoto
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Patent number: 7382037Abstract: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.Type: GrantFiled: September 28, 2005Date of Patent: June 3, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Mitsuo Umemoto, Kojiro Kameyama, Akira Suzuki
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Patent number: 7364941Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.Type: GrantFiled: August 19, 2005Date of Patent: April 29, 2008Assignees: Sanyo Electric Co., Ltd., Kanto SANYO Semiconductors Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
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Patent number: 7365628Abstract: A semiconductor apparatus having a semiconductor chip, a first coil electrically connected to the semiconductor chip and a first electrode electrically connected to the first coil is comprised of a second electrode which can be electrically connected to the first electrode as well as which can be electrically connected to a second coil on the outside of the semiconductor apparatus, and is characterized by that inductance composed of the first coil and the second coil is obtained by electrically connecting the second electrode to the first electrode and the second coil.Type: GrantFiled: January 24, 2006Date of Patent: April 29, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Akihiro Sato, Satoru Sekiguchi, Kiyokazu Kamado, Makoto Tsubonoya, Kiyoshi Mita, Yoichi Nabeta