Patents Assigned to Kanto Sanyo Semiconductors Co., Ltd.
  • Publication number: 20050161251
    Abstract: To provide a hybrid integrated circuit device in which the rear surface of a circuit board is exposed to the outside and a method of manufacturing the same. Here, leads are fixed to the surface of the circuit board along one side thereof. A method of manufacturing a hybrid integrated circuit device includes the steps of forming an electric circuit which includes a conductive pattern formed on a surface of a circuit board and a circuit element electrically connected to the conductive pattern, fixing a lead to a pad formed of the conductive pattern, housing the circuit board in a cavity of molds, and fixedly supporting the lead by clamping the lead between the molds, and performing sealing by filling inside of the cavity with sealing resin with the rear surface of the circuit board made in contact with an inside bottom surface of the molds.
    Type: Application
    Filed: December 22, 2004
    Publication date: July 28, 2005
    Applicants: SANYO ELECTRIC CO., LTD., KANTO SANYO SEMICONDUCTORS CO., LTD.
    Inventors: Haruhiko Mori, Masaru Kanakubo, Hideyuki Sakamoto
  • Publication number: 20050161782
    Abstract: Provided are a hybrid integrated circuit device and a manufacturing method of the same, in which it is capable of molding while fixing a position of a board in a cavity. A method for manufacturing a hybrid integrated circuit device includes the steps of: forming an electric circuit which includes a conductive pattern formed on a surface of a circuit board, and a circuit element electrically connected to the conductive pattern; fixing a tip portion of a lead to a pad formed of the conductive pattern disposed along a side of the circuit board, the tip portion being fixed approximately perpendicularly to a surface direction of the circuit board; housing the circuit board in a cavity of molds, and allowing a rear surface of the circuit board to abut with a bottom of the cavity by clamping the lead between the molds; and performing sealing by filling inside of the cavity with a sealing resin to expose the rear surface of the circuit board to the outside.
    Type: Application
    Filed: December 22, 2004
    Publication date: July 28, 2005
    Applicants: SANYO ELECTRIC CO., LTD., KANTO SANYO SEMICONDUCTORS CO., LTD.
    Inventor: Masaru Kanakubo
  • Patent number: 6919624
    Abstract: It is difficult to check the mounted state of solder by means of visual inspection after the mounting of a semiconductor device according to a conventional art, in particular, a CSP-semiconductor device, to a substrate and a problem arises wherein defective products increase and yield decreases. Terminals 50, 51, 52 and 53 for external connection are exposed from second main surface 412 of first insulating substrate 41 in the semiconductor device according to the present invention. Thus, second insulating substrate 48 is adhered to second main surface 412 so as to surround the internal portions of these terminals for external connection. Thereby, second insulating substrate 48 serves as a background mirror so that the mounted state of deep portions of the solder can be ascertained at the time of visual inspection of the mounted state of solder after the mounting of the semiconductor device to the substrate.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: July 19, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Takayuki Tani, Takao Shibuya
  • Publication number: 20040121562
    Abstract: A semiconductor device manufacturing method comprises a step of forming a laminated structure by adhering, on a semiconductor substrate including a plurality of integrated circuits, a carrier member covering a region in which the plurality of integrated circuits are formed, with an insulating resin interposed between the semiconductor substrate and the carrier member, a step of cutting a notch into the laminated structure so as to cut the semiconductor substrate together with the insulating resin while allowing at least a portion of the carrier member to remain uncut, and a dicing step for dividing the laminated structure by cutting the carrier member. The notch cutting step is performed while cooling a dicing saw used to cut the semiconductor substrate.
    Type: Application
    Filed: November 14, 2003
    Publication date: June 24, 2004
    Applicants: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Motoaki Wakui, Kaoru Sasaki, Kenji Imai, Hiroyuki Shinogi, Takashi Noma