Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

Abstract: A semiconductor device includes a source region and a drain region formed on a substrate; a gate structure formed between the source region and the drain region; a field insulating layer formed between the gate structure and the drain region; a first field plate structure formed on the field insulating layer, formed on a same plane and material as the gate structure; a source metal wiring connected to the source region, the first field plate structure, and the second field plate structure; a drain metal wiring connected to the drain region; and an interlayer insulating layer formed under the source metal wiring and the drain metal wiring; and a second field plate structure formed on the interlayer insulating layer, formed between the first field plate structure and the drain region, and formed of a material different from a material of the first field plate structure.

Abstract: A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

Abstract: A bidirectional I/O circuit includes an output post driver configured to control an output signal of a bidirectional pad during a normal mode, a floating N-well network configured to apply a VDD-level bias to the output post driver based on an input signal of the bidirectional pad during a power down mode, and a post driver control circuit configured to set an input voltage level of the output post driver to a VDD level during the power down mode to prevent a leakage current path from being formed through the output post driver. A parasitic diode is formed between the drain of the first PMOS transistor and an N-well of the first PMOS transistor. The N-well of the first PMOS transistor is connected to the floating N-well network, and the source and the N-well of the first PMOS transistor are not physically connected to each other.

Abstract: A semiconductor device includes a first source region and a drain region disposed on a substrate; a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region; a first select gate disposed on one sidewall of the first gate stack; a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region; a second spacer disposed on an upper sidewall of the first select gate; a first control gate silicide layer disposed on the first control gate; and a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.

Abstract: A method for manufacturing a semiconductor device includes providing a high-voltage isolation capacitor region on a substrate, forming a bottom electrode in the high-voltage isolation capacitor region, forming an inter-metal dielectric layer on the bottom electrode, forming a low bandgap dielectric layer on the inter-metal dielectric layer, forming a first hard mask layer on the low bandgap dielectric layer, patterning the first hard mask layer and the low bandgap dielectric layer to form a patterned first hard mask layer and a patterned low bandgap dielectric layer, depositing a thick metal film on the patterned first hard mask layer and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top electrode in the high-voltage isolation capacitor region, such that the top electrode overlaps the patterned first hard mask layer and the patterned low bandgap dielectric layer.

Abstract: A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

Abstract: A manufacturing method for a semiconductor device, includes: forming a first gate structure and a second gate structure on a substrate; forming a deep trench isolation (DTI) hard mask on the first and second gate structures; forming a deep trench isolation disposed between the first gate structure and the second gate structure; depositing a first undoped oxide layer in the deep trench isolation; performing a first etch-back process on the first undoped oxide layer to remove a portion of the undoped oxide layer; depositing a first deep trench isolation (DTI) gap-fill layer on a remaining portion of the undoped oxide layer, and performing a second etch-back process on the first DTI gap-fill layer; depositing a second DTI gap-fill layer to seal the deep trench isolation, and forming a planarized second DTI gap-fill layer by a planarization process; and depositing a second undoped layer on the planarized second DTI gap-fill layer.

Abstract: A semiconductor device includes a device region, including a source contact, a drain contact formed on a substrate, and a gate contact formed between the source contact and the drain contact; an isolation region surrounding the device region, the isolation region including an N-type semiconductor region formed on the substrate, a first silicide layer and a second silicide layer formed in the N-type semiconductor region and separated from each other by an isolation layer, and an anode contact and a cathode contact connected to the first silicide layer and the second silicide layer, respectively; and a Schottky barrier diode formed inside the isolation region by a junction of the first silicide layer and the N-type semiconductor region. The anode contact is connected to the source contact, and the cathode contact is connected to the drain contact.

Abstract: A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

Abstract: The analog-to-digital converter (ADC) includes a sample and hold circuit configured to sample an analog input voltage and hold the sampled voltage. The sample and hold circuit includes: an analog switch configured to generate a boosting voltage obtained by adding a constant voltage to the analog input voltage, and output an analog output voltage corresponding to the analog input voltage by using the boosting voltage; and a capacitor in which the analog output voltage is charged.

Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A negative voltage switching device includes a first switching circuit configured to transmit a first negative voltage, a second switching circuit configured to transmit a second negative voltage, and a switching selection circuit configured to select one of the first switching circuit or the second switching circuit for transmitting one of the first negative voltage and the second negative voltage to an output terminal.

Abstract: A semiconductor device including a high-voltage isolation capacitor and a mixed-signal integrated circuit, wherein the high-voltage isolation capacitor includes bottom electrodes, each spaced apart from another, disposed on a substrate; top electrodes disposed on corresponding ones of the bottom electrodes; an inter-metal dielectric layer disposed between the bottom electrodes and the top electrodes; and low bandgap dielectric layers disposed on the inter-metal dielectric layer. Each of the low bandgap dielectric layers is disposed below corresponding ones of the top electrodes, and the low bandgap dielectric layers are absent in the mixed-signal integrated circuit.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a high-voltage isolation capacitor region and a mixed-signal integrated circuit region on a substrate, forming a bottom electrode on the high-voltage isolation capacitor region, forming a bottom metal line on the mixed-signal integrated circuit region, forming an inter-metal dielectric layer on the bottom electrode and the bottom metal line, forming a top via in the inter-metal dielectric layer, forming a low bandgap dielectric layer on the top via and the inter-metal dielectric layer, patterning the low bandgap dielectric layer to form a patterned low bandgap dielectric layer, depositing a thick metal film on the top via and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top metal line on the high-voltage isolation capacitor region and form a top electrode on the mixed-signal integrated circuit region.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.

Abstract: A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

Abstract: A manufacturing method for a deep trench, the method includes forming a first trench in a substrate and performing a first cycle and a second cycle. Each comprising performing a passivation operation forming a passivation film on a sidewall and a bottom surface of the first trench, performing a first etching with a first bias power to remove the passivation film formed on the bottom surface of the first trench to expose the bottom surface of the first trench, and performing a second etching with a second bias power etching the exposed bottom surface of the first trench to form a second trench disposed below the first trench. The first bias power and the second bias power in the second cycle is greater than the first bias power and the second bias power in the first cycle, respectively.