Patents Assigned to KEY FOUNDRY CO., LTD.
  • Patent number: 11024398
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 1, 2021
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11018060
    Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 25, 2021
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Yang Beom Kang, Kang Sup Shin
  • Publication number: 20210125678
    Abstract: An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.
    Type: Application
    Filed: August 14, 2020
    Publication date: April 29, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min CHO, Sung Bum PARK, Kee Sik AHN, Seong Jun PARK
  • Publication number: 20210125677
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Application
    Filed: April 15, 2020
    Publication date: April 29, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min CHO, Sung Bum PARK, Kee Sik AHN, Seong Jun PARK
  • Patent number: 10985074
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Key Foundry Co., Ltd
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Patent number: 10978587
    Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 13, 2021
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Yu Shin Ryu, Tae Hoon Lee, Bo Seok Oh
  • Publication number: 20210104630
    Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: April 8, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Jin Seong CHUNG, Tae Hoon LEE
  • Publication number: 20210082938
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 18, 2021
    Applicant: Key Foundry Co., Ltd.
    Inventors: Su Jin KIM, Hye Jin YOO
  • Patent number: 10950614
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 16, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Su Jin Kim, Hye Jin Yoo
  • Publication number: 20210066134
    Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Yang Beom KANG, Kang Sup SHIN
  • Patent number: 10923603
    Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 16, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Yon Sup Pang, Hyun Kwang Shin, Tae Hoon Lee
  • Patent number: 10916419
    Abstract: Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material; and a second electrode disposed on the insulator.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 9, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Kwan-Soo Kim, Soon-Wook Kim
  • Publication number: 20210028298
    Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.
    Type: Application
    Filed: January 21, 2020
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Hyun Kwang SHIN, Jung Hwan LEE
  • Publication number: 20210028166
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Application
    Filed: November 13, 2019
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang SHIN
  • Publication number: 20210028183
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Application
    Filed: February 26, 2020
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il KIM, Yang Beom KANG, Jung Hwan LEE, Min Kuck CHO, Hyun Chul KIM
  • Publication number: 20210005622
    Abstract: A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.
    Type: Application
    Filed: January 7, 2020
    Publication date: January 7, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck CHO, Seung Hoon LEE
  • Patent number: 10867677
    Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 15, 2020
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin Kim, Myeong Seok Kim, In Chul Jung, Young Bae Kim, Seung Guk Kim, Jung Hwan Lee