Abstract: The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer readable instructions, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a negative pulse generator which is adapted to reduce the charge on capacitor in one or more volatile memory cells to zero logic by using a switch connected to the Voltage Reference (Vref) of the volatile memory cell, a controller and a negative power supply. The switch and the negative power supply impose a negative pulse on the Vref of the volatile memory cells on being instructed by the controller at the occurrence of a predefined event. An erasure module associated with the controller is provided for instructing the erasure circuitry for erasing data at the occurrence of a predefined event.

Abstract: A vibrational energy harvesting system is disclosed. Included is a first energy harvesting unit and a second energy harvesting unit that convert mechanical vibrations into first and second AC signals, respectively. A first AC-DC converter coupled to the first energy harvesting unit and a second AC-DC converter coupled to the second energy harvesting unit are configured to convert the first AC signal and the second AC signal into a first DC signal and a second DC signal, respectively. A DC-DC converter is coupled between the second AC-DC converter and a controller, and is configured to receive the second DC signal and provide a regulated DC signal by using energy from the second DC signal in response to a periodic signal generated by the controller. Typically, an energy storage unit is coupled to the DC-DC converter and is configured to receive and store energy from the regulated DC signal.

Abstract: An architecture for linear-time extraction of maximally stable extremal regions (MSERs) having an image memory, heap memory, a pointer array and processing hardware is disclosed. The processing hardware is configured to in real-time analyze image pixels in the image memory using a linear-time algorithm to identify a plurality of components of the image. The processing hardware is also configured to place the image pixels in the heap memory for each of the plurality of components of the image, generate a pointer that points to a location in the heap memory that is associated with a start of flooding for another component and store the pointer in the array of pointers. The processing hardware is also configured to access the plurality of components using the array of pointers and determine MSER ellipses based on the components and MSER criteria.

Abstract: A medical device and method for detecting a ventricular arrhythmia event is disclosed. The medical device includes input circuitry configured to receive an electrocardiogram (ECG) signal, processing circuitry coupled to the input circuitry and configured to identify at least one fiducial point of a first heartbeat signature and at least fiducial point of a second heartbeat signature of the ECG signal, and feature extraction circuitry coupled to the processing circuitry. The feature extraction circuitry is configured to determine at least one difference between the at least one fiducial point of the first heartbeat signal and the at least one fiducial point of the second heartbeat signal. Machine learning circuitry is coupled to the feature extraction circuitry and is configured to select a ventricular arrhythmia class based on the at least one difference.

Abstract: This invention relates to methods for storing and searching data. Embodiments of the invention make use of suffix trees to support binary pattern matching. Embodiments of the invention can be shown to have comparable search speeds to searches of known suffix trees, but are advantageous in that they have lower memory usage requirements which is important in large data environments.

Abstract: The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.

Abstract: This invention relates to methods and devices for time transfer. The invention has particular application in the alignment of slave clocks to a master clock and dealing with packet delay variations. In embodiments of the invention, the slave clock uses the residence times measured by end-to-end transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

Abstract: This invention relates to methods and systems for estimating and checking synchronization accuracy, in particular frequency synchronization accuracy. It is particularly applicable to synchronization methods and systems which involve a digital phase-locked loop (DPLL) and embodiments provide methods and systems for estimating and tracking how well the DPLL is frequency synchronized to a source frequency. In one embodiment, frequency synchronization accuracy is used as an additional quality metric for mobile call handover between base stations. Call handover is of major importance within any mobile network; without checking frequency synchronization before handover dropped calls and interrupted communication can result.

Abstract: This invention relates to methods and devices for time synchronization. The invention has particular application in the alignment of slave clocks to a master clock and in dealing with packet delay variation and dynamic asymmetries in the network links between them. In embodiments of the invention, the slave clock uses the peer link delay and residence times measured by peer-to-peer transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

Abstract: This invention relates to methods and systems for controlling consumption, particularly power consumption, more particularly by appliances in a building, and is generally suitable for integration with building management systems. Embodiments of the invention provide methods and systems which probabilistically limit the aggregated power load of a plurality of climate control appliances in a building to a selected value, while seeking to minimize the deviation from target environmental conditions within the building. The embodiments of the invention propose distributed decision-making by individual devices based on projected deviation from the target conditions after a period of activity or inactivity.

Abstract: The invention relates to a method and system that provide a continuous querying mechanism that analyses real-time data streams to generate relevant results. It leverages data grid and event processing technology to provide a high performance and extremely scalable continuous querying solution. An embodiment of the invention provides a flexible querying language and data storage to allow users to register their interest in specific types of data, e.g. processes. The users are notified of matching results using an event-based mechanism. In order to efficiently analyze a large amount of data, the embodiment uses a grid infrastructure that allows storage of the data across many grid nodes and distributes the query execution workload, avoiding the bottleneck represented by constantly querying a database. Continuous queries are stored in a Continuous Query Registry and that Registry is invoked every time an insert or update event occurs on the triple store.

Abstract: The invention relates to a method and system that provide a high performance and extremely scalable triple store within the Resource Description Framework (or alternative data models), with optimized query execution. An embodiment of the invention provides a data storage and analysis system to support scalable monitoring and analysis of business processes along multiple configurable perspectives and levels of granularity. This embodiment analyses data from processes that have been already executed and from ongoing processes, as a continuous flow of information. This embodiment provides defining and monitoring processes based on no initial domain knowledge about the process and such that the process will be built only from the incoming flow of information. Another embodiment of the invention provides a grid infrastructure that allows storage of data across many grid nodes and distribution of the workload, avoiding the bottleneck represented by constantly querying a database.

Abstract: Methods and systems for detecting and/or tracking one or more objects utilize depth data. An example method of detecting one or more objects in image data includes receiving depth image data corresponding to a depth image view point relative to the one or more objects. A series of binary threshold depth images are formed from the depth image data. Each of the binary threshold depth images is based on a respective depth. One or more depth extremal regions in which image pixels have the same value are identified for each of the binary depth threshold images. One or more depth maximally stable extremal regions are selected from the identified depth extremal regions based on change in area of the one or more respective depth extremal regions for different depths.

Abstract: Architecture for real-time extraction of maximally stable extremal regions (MSERs) is disclosed. The architecture includes communication interface and processing circuitry that is adapted in hardware to receive a data streams of an intensity image and a depth image in real-time and provide intensity labels for image regions within the intensity image that match a given intensity threshold and provide depth labels for image regions within the depth image that match a given depth threshold. The processing circuitry is also adapted in hardware to find intensity extremal regions within the intensity image based upon the intensity labels and to find depth extremal regions within the depth image based upon the depth labels. The processing circuitry determines strong extremal regions based upon significant overlap between the intensity extremal regions and depth extremal regions. The processing circuitry then determines X-MSER ellipses parameters based upon the strong extremal regions and X-MSER criteria.

Abstract: There is provided a computer-implemented method of estimating transmitted signals in a communication system, the signals being transmitted by a transmitter to a receiver over a communication channel having a channel response, the method comprising estimating the transmitted signals based on generated trial sequences minimizing the channel response between adjacent received signals. There is also provided a receiver, a signal detector device and a communication system adapted to estimated transmitted signals in a communication system by generating trial sequences and determining the generated trial sequences minimizing the channel response between adjacent received signals. The present invention is particularly adapted for OFDM communication systems.

Abstract: This invention relates to methods and systems for estimating skew based on, for example, the IEEE 1588 Precision Time Protocol (PTP). These methods and systems can allow the clock skew between a master clock (server) and slave clock (client) exchanging PTP messages over a packet network to be estimated. In one embodiment, the slave employs a digital phase-locked loop (DPLL) driven by timestamps supplied from a master clock. The slave is able to process the timestamp information embedded in PTP Sync and Follow_Up messages in order to lock its frequency to that of the master clock. In certain embodiments a frequency locked DPLL and a local free-running counter are used to estimate the skew of the local slave oscillator.

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

Abstract: The present invention proposes a demodulator device, a receiver and a demodulation method for M-ary amplitude shift keying systems (MASK) that requires partial knowledge of the CSI, namely, the channel attenuation coefficient. Therefore, the new demodulator, receiver and demodulation method do not require the knowledge of the channel phase shift. Consequently, no complicated channel estimation techniques are required, and the system will be very robust to the system impairments such as phase noise, I-Q imbalance, etc. In this sense, the new technique is denoted as semi-coherent demodulation (SCD). To reduce the complexity of the new SCD, a suboptimal demodulator is derived which has much lower complexity than the optimal while providing almost the same error probability.

Abstract: In response to requests for their use of the resources by the applications, resources are first allocated to “inelastic” requests specified for performance at a specific time slot. A baseline allocation of resources is then determined which is the minimum amount of capacity that has to be used for efficient operation of the resources required to meet the requests. This baseline will include some additional capacity as the minimum efficient capacity is less than the maximum capacity. “Elastic” requests, specified for performance within a predetermined time range comprising two or more of the set of time slots, are then allocated so as to prioritize the use of this spare capacity, bringing actual usage up to at least the baseline allocation of resources. If further capacity is required to meet all the inelastic requests, further capacity is allocated and the baseline redefined to include it.

Abstract: Hardware architecture for real-time extraction of maximally stable extremal regions (MSERs) is disclosed. The architecture includes a communication interface and processing circuitry that are configured in hardware to receive a data stream of an intensity image in real-time and provide labels for image regions within the intensity image that match a given intensity threshold. The communication interface and processing circuitry are also configured in hardware to find extremal regions within the intensity image based upon the labels and to determine MSER ellipses parameters based upon the extremal regions and MSER criteria. In at least one embodiment, the MSER criteria include minimum and maximum MSER areas, and an acceptable growth rate value for MSER area. In another embodiment, the MSER criteria include a nested MSER tolerance value.