Patents Assigned to Kioxia Corporation
  • Publication number: 20240087853
    Abstract: A plasma processing apparatus includes: a processing chamber that is capable of processing a substrate; a stage that is provided in the processing chamber and on which the substrate is placeable; a plasma generator that is provided at an upper portion of the processing chamber and supplies plasma to the processing chamber; a first shielding plate that is provided at an upper side of the processing chamber, faces the substrate placed on the stage, has an opening in at least a part of a position overlapping an outer peripheral portion of the substrate in an up-down direction, and shields the substrate from the plasma at the upper portion of the processing chamber; and an adjustment mechanism that is capable of rotating at least one of the substrate and the first shielding plate and relatively moves a position of the opening of the first shielding plate with respect to a peripheral direction of the substrate.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventor: Kazuhiko NAKAMURA
  • Publication number: 20240090203
    Abstract: A semiconductor storage device includes a first oxide semiconductor layer that extends in a first direction; a second oxide semiconductor layer that extends in the first direction and is adjacent to the first oxide semiconductor layer in a second direction intersecting to the first direction; first wiring that extends in a third direction intersecting to the first direction and overlaps with the first oxide semiconductor layer in the third direction; second wiring that extends in the third direction and overlaps with the second oxide semiconductor layer in the third direction; a first insulating film that is provided between the first wiring and the first oxide semiconductor layer; a second insulating film that is provided between the second wiring and the second oxide semiconductor layer; a first conductor that is provided on the first oxide semiconductor layer; a second conductor that is provided on the second oxide semiconductor layer; and an insulating layer that has a gap between the first conductor and
    Type: Application
    Filed: August 25, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Takanori AKITA, Kotaro NODA, Seiichi URAKAWA, Mutsumi OKAJIMA
  • Publication number: 20240090239
    Abstract: A semiconductor device includes a metal layer disposed above a transistor on a first substrate. The metal layer includes a first region extending in a first direction and a second region that has a width in the first direction smaller than the first region and protrudes from the first region in a second direction, and has a first corner portion having an angle larger than 180° as viewed in a third direction between a proximal end portion of the second region and the first region. The metal layer includes a first portion that is disposed within the first region and has a lower surface at a first height, and a second portion that is disposed within the second region and has a lower surface at a second height lower than the first height.
    Type: Application
    Filed: March 1, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Kiichi TACHI, Ryota NIHEI, Yoshikazu HOSOMURA
  • Publication number: 20240088941
    Abstract: According to one embodiment, a file transmission/reception device includes a communication direction managing unit and an application unit. The communication direction managing unit, in near field communication, cuts off a connection with an opposing device in a case where a conflict occurs with the opposing device, and, after being reconnected to the opposing device, switches the file transmission/reception device to any one mode of a master mode and a slave mode. The application unit performs transmission, reception, or transmission/reception of a file between the opposing device and the file transmission/reception device in the master mode or the slave mode in accordance with a mode specified by the communication direction managing unit.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yoshinari KUMAKI, Hidetomo MATSUO, Kazuya NARA
  • Publication number: 20240082878
    Abstract: A scrap collection device according to the embodiment includes a mesh conveyor, a peeler, and one or more collection containers. The mesh conveyor includes a mesh belt configured to receive a fluid mixture of a liquid and scraps from above to trap at least a portion of the scraps and to allow the liquid to pass, and moves the mesh belt. The peeler peels the scraps from a face of the mesh belt in a state where the face of the mesh belt is directed downward. The collection containers collect the peeled scraps.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventor: Shinji OOKA
  • Publication number: 20240090125
    Abstract: A circuit board is a wiring board frame in which a plurality of wiring boards in each of which a pair of lands electrically connected to a capacitor are formed on a first surface are arranged side by side. In the wiring board frame, an inspection path is formed. The inspection path passes between the pair of lands provided on each of the plurality of wiring boards. The inspection path includes a first wiring including one end between the pair of lands, and a second wiring including one end between the pair of lands, and the one end of the first wiring and the one end of the second wiring are formed to be separated from each other.
    Type: Application
    Filed: March 7, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Takashi YAMAMOTO, Soichiro IBARAKI
  • Publication number: 20240087656
    Abstract: A semiconductor memory device includes a first memory cell transistor, a first bit line electrically coupled to the first memory cell transistor, a first sense amplifier, and a first latch circuit. The first sense amplifier includes a first node coupled to the first bit line, a first transistor including one end electrically coupled to the first latch circuit, a second node coupled to a gate of the first transistor, and a second transistor coupled between the first and second nodes. The second transistor is in an ON state during an operation of transferring a charge from the first bit line to the first and second nodes in accordance with data of the first memory cell transistor. The second transistor is in an OFF state during an operation of transferring data of the second node to the first latch circuit.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Katsuaki ISOBE, Takeshi HIOKA, Mario SAKO
  • Publication number: 20240084456
    Abstract: In one embodiment, a film forming apparatus includes a chamber configured to load a substrate, a stage configured to support the substrate, and a gas supplier configured to supply a gas into the chamber to form a film on the substrate. The device further includes a first detector configured to detect a first value that varies depending on at least pressure of a first portion above the stage in the chamber, and a controller configured to control a process of forming the film on the substrate based on the first value.
    Type: Application
    Filed: June 9, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazuhiro KATONO, Kazuhiro MATSUO, Yusuke MIKI, Kenichiro TORATANI, Akifumi GAWASE
  • Publication number: 20240086280
    Abstract: A memory system includes a non-volatile memory and a memory controller that encodes data with an error correction code and stores the encoded data in the non-volatile memory. The memory controller executes first processing which is at least a part of first decoding processing using read information read from the non-volatile memory, uses statistical information of a processing result of the first processing to estimate a first indicator indicating a ratio of hard errors among bit errors in the read information, determines parameters for second decoding processing having a higher latency than the first processing according to the first indicator, and executes the second decoding processing by using the determined parameters and the read information.
    Type: Application
    Filed: February 13, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Takahiro KUBOTA, Hironori UCHIKAWA
  • Publication number: 20240086099
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Publication number: 20240086653
    Abstract: A memory card socket includes a first pad provided in a first face of a first substrate; a first terminal having a first end portion that contacts a terminal of a memory card and a second end portion electrically connected to the first pad; a holder provided on the first face and fixing the first terminal to the first substrate; and a protrusion provided on the first face, having a second face that contacts a portion of the memory card that excludes the terminal, and including a metal material or an insulating material.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventor: Akihiro IIDA
  • Publication number: 20240086077
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.
    Type: Application
    Filed: March 10, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Toshio FUJISAWA, Keisuke NAKATSUKA
  • Publication number: 20240087616
    Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Takafumi MASUDA, Nobuyoshi SAITO, Mutsumi OKAJIMA, Keiji IKEDA
  • Publication number: 20240086096
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yuki SASAKI, Shinichi KANNO
  • Publication number: 20240087629
    Abstract: According to one embodiment, a memory device includes first interconnects in a first direction, second interconnects in a second direction intersecting the first direction, and memory cells. Each of the memory cells is associated with a set of one of the first interconnects and one of the second interconnects between the first interconnects and the second interconnects and includes a variable resistance element and a switching element which are coupled in series. A forming method of the memory device includes: selecting a memory cell having a highest interconnect resistance from memory cells on which a forming process has not been performed; performing a forming process on a switching element in the selected memory cell; and repeating the selecting and the performing on the memory cells.
    Type: Application
    Filed: March 7, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventor: Naoki MATSUSHITA
  • Publication number: 20240087649
    Abstract: A semiconductor memory device according to an embodiment includes: a driver for supplying a voltage, the driver in the first step, when a current flows through the first substring, the second substring, the third substring, or the fourth substring, performing a second step of applying the first voltage to the bit line, applying a fourth voltage higher than the third voltage to the third select gate line, the fourth select gate line, the fifth select gate line, and the sixth select gate line, and applying a fifth voltage higher than the third voltage and lower than the fourth voltage to the first word lines and the second word lines.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Sumiko DOMAE, Kyosuke SANO
  • Publication number: 20240086111
    Abstract: The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.
    Type: Application
    Filed: March 2, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Yu NAKANISHI, Kazuhiro HIWADA
  • Publication number: 20240088152
    Abstract: A semiconductor device of an embodiment includes N-wells and P-wells extending in a first direction and alternately arranged in a second direction orthogonal to the first direction; and a dummy gate formed above the N-wells and the P-wells so as to extend across at least one boundary between an N-well and a P-well that are adjacent to each other, the dummy gate being not connected to a wire, in which the dummy gate is formed in a region other than an end portion in the first direction of, among the N-wells and the P-wells, a well that has a width smaller than a predetermined threshold in the second direction.
    Type: Application
    Filed: July 31, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Tomoaki SHINO, Mitsuhiro NOGUCHI, Takayuki TOBA
  • Publication number: 20240087970
    Abstract: According to one embodiment, a semiconductor device includes a wiring board, an adhesive, a semiconductor module, and a sealing member. The wiring board includes a step at an outer peripheral. The adhesive is provided on the wiring board. The semiconductor module is disposed on the adhesive. The semiconductor module is mounted inward from the step of the wiring board. The sealing member covers the step, a side surface of the adhesive, and the semiconductor module. The step includes a side surface and a bottom surface. The side surface faces an outside of the wiring board. The bottom surface extends from a lower end of the side surface toward an end part of the wiring board. The side surface of the step and the side surface of the adhesive are positioned to overlap with one another in a view from a stacking direction of the adhesive and the semiconductor module.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Takeori MAEDA, Tetsuya KUROSAWA
  • Patent number: 11928364
    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to queue write commands received from a host. The commands may include a first write command to write first write data associated with a first stream and a second write command to write second write data associated with a second stream. When the first and second write commands are queued, the memory controller repeatedly performs a sequence of a first operation of acquiring a predetermined amount of the first write data from the host and then transmitting to the non-volatile memory, and a second operation of acquiring the predetermined amount of the second write data from the host and then transmitting to the non-volatile memory. The second operation in the sequence is started after completion of the first operation in the sequence.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: March 12, 2024
    Assignee: Kioxia Corporation
    Inventor: Hotaka Ueki