Abstract: An inspection result analysis device includes a processor. The processor factorizes each first distribution of a first distribution group into a second distribution group and a weight group corresponding to the second distribution group by non-negative matrix factorization of the first distribution group. Each first distribution is a distribution of numerical data on a surface of a substrate, the numerical data resulting from an inspection of the substrate. The processor generates a fourth distribution by multiplying a third distribution by a weight corresponding to the third distribution to acquire a representative value of a numerical data group constituting the fourth distribution. The processor associates a fifth distribution with the third distribution when the representative value exceeds a threshold. The fifth distribution is one first distribution of the first distribution group.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: According to one embodiment, a memory system includes a non-volatile memory including a plurality of physical blocks and a controller. The controller is configured to allocate the plurality of physical blocks to a plurality of first block sets each including physical blocks among the plurality of physical blocks, generate a plurality of groups obtained by grouping the plurality of first block sets by the number of defective physical blocks included in each of the plurality of first block sets, and select a plurality of the first block sets from at least two groups of the plurality of groups to generate a second block set from the plurality of selected first block sets.

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

Abstract: A measurement device includes a first light source configured to generate first light; a first beam splitter configured to split the first light into second light and third light; and a detector configured to receive signal light generated from a subject through irradiating the subject with the second light and the third light. The first light has a wavelength transmittable through a substrate. The second light is vertically incident on a surface of a first film formed on the subject. The third light is vertically incident on a rear surface of the substrate to be coaxial with the second light. A phase of transmitted light through the substrate is opposite to a phase of reflected light. An intensity of the transmitted light is equal to an intensity of the reflected light.

Abstract: According to one embodiment, a storage device includes a stacked layer structure including a switching element, an electrode including a first electrode portion, and a variable resistance element, which are stacked in a first direction, wherein the switching element and the electrode are in contact with each other in the first direction, and a first face of the first electrode portion on a side of the switching element is in contact with a second face that is inside the stacked layer structure and that is larger than the first face.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; a second semiconductor layer provided above the first semiconductor layer; a third semiconductor layer interposed between the first and second semiconductor layers; a stacked body provided above the second semiconductor layer, in which a plurality of conductive layers are stacked one by one while being separated from each other; and a pillar including a channel layer that extends through the stacked body, the second semiconductor layer, and the third semiconductor layer in a stacking direction of the stacked body and reaches a predetermined depth of the first semiconductor layer. The channel layer is electrically connected to the third semiconductor layer on a side surface.

Abstract: A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a first insulating layer adjacent to the transistor in a first direction along a main surface of the semiconductor substrate, the first insulating layer being formed toward an inside of the semiconductor substrate; a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; a second insulating layer disposed between the first insulating layer and the first conductive layer; and a first semiconductor layer disposed between the second insulating layer and the first conductive layer.

Abstract: According to one embodiment, a semiconductor product evaluation data management system includes a computer server that manages evaluation data of a semiconductor product and a plurality of storage devices that store the evaluation data. The computer server includes a storage data index file configured to store an index attached to the evaluation data to be stored in the computer server and the plurality of storage devices; a storage data index updating unit configured to store and update manufacturing information of semiconductor product in the index; and a storing method updating unit configured to control movement of the evaluation data to a specific storage device among the plurality of storage devices in a unit of the manufacturing information of the semiconductor product in accordance with the index.

Abstract: A semiconductor device includes: an oxide semiconductor including a first end and a second end and extending in a first direction oriented from the second end to the first end; a first electrode configured to come into contact with the first end of the oxide semiconductor; a second electrode configured to come into contact with the second end of the oxide semiconductor; a gate electrode configured to enclose the oxide semiconductor with a first insulating film interposed therebetween between the first and second ends of the oxide semiconductor; and a metal film including a cylindrical portion that comes into contact with the gate electrode in the first direction and encloses the oxide semiconductor with the first insulating film interposed therebetween.

Abstract: A semiconductor device of an embodiment includes: first and second regions that are provided in a substrate, the first and second regions containing impurities of a first conductivity type; a gate electrode disposed above the substrate between the first and second regions; first and second metal silicide layers disposed in the first and second regions, respectively; and first and second contacts connected to the first and second regions via the first and second metal silicide layers, respectively, in which the first and second contacts include: first and second oxidized silicide layers that are disposed at lower end portions of the first and second contacts and contain a predetermined metal different from metals included in the first and second metal silicide layers, respective; and metal layers that are in contact with the first and second oxidized silicide layers and extend in a second direction that intersects the first direction, respectively.

Abstract: A semiconductor manufacturing apparatus includes a storage device configured to store first location information of a plurality of first lines on a first surface of a semiconductor wafer to be cut, and further store second location information of a second line not to be cut among the plurality of first lines; and a cutter configured to cut the semiconductor wafer along one or more of the plurality of first lines other than the second line. The semiconductor wafer is configured to be cut into a plurality of semiconductor chips.

Abstract: According to one embodiment, a memory system includes a buffer, a nonvolatile memory and a controller. The buffer is capable of storing packets up to a first upper limit number. The controller generates a packet related to access to the nonvolatile memory and stores the packet in the buffer. The controller classifies the packets into packets of a first type and packets of a second type. The number of packets of the second type allowed to be stored in the buffer is limited to a second upper limit number smaller than the first upper limit number. When the number of packets of the second type stored in the buffer is the second upper limit number or larger, the controller does not generate a second packet of the second type or does not store the second packet in the buffer.

Abstract: A memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of word lines, a plurality of bit lines, and a plurality of storage elements. The control circuit includes an ECC circuit that detects and corrects a data error stored in the plurality of storage elements, acquires first data by reading data stored in the plurality of storage elements of a page connected to the same word line with a first read voltage, acquires second data obtained by correcting the first data when the first data can be corrected by the ECC circuit, and writes data based on the second data to the plurality of storage elements of the page.

Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

Abstract: A solid-state storage device is provided, which is electrically connected to a host. The solid-state storage device includes a controller, a volatile memory, and a non-volatile memory. The controller divides the non-volatile memory into a plurality of functional regions. The controller sets a functional-region weight value corresponding to a priority of each functional region, and uses a weighted round robin mechanism to perform a number of access commands for each functional region according to the functional-region weight value of each functional region. The controller sets a submission-queue weight value corresponding to each submission queue within each functional region.

Abstract: A solid-state storage device is provided. The solid-state storage device is electrically connected to a host. The solid-state storage device includes a controller, a cache memory, a volatile memory, and a non-volatile memory. The cache memory, the volatile memory, and the non-volatile memory are electrically connected to the controller. The cache memory includes a first region and a second region. The controller is configured to fetch an access command from the host, and to store the access command in the first region. The controller is further configured to back up the access command stored in the first region to the volatile memory. The controller is further configured to store the access command backed up in the volatile memory in the second region, and to execute the access command stored in the second region.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.