Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: A manufacturing method of a semiconductor device includes stacking a first film on a first substrate and stacking a third film and a second film on a second substrate; joining a main surface on an opposite side of the first substrate of the first film and a main surface on an opposite side of the second substrate of the second film; emitting infrared laser light from a side of the second substrate in such a manner that a focal point is placed in a vicinity of the second film; and peeling off the second substrate. Absorptance of the infrared laser light of the second film is higher than absorptance of the infrared laser light of the second substrate, and a thermal expansion coefficient of the third film is different from a thermal expansion coefficient of a film in contact with the third film.

Abstract: A method for manufacturing a semiconductor device includes preparing a substrate having a film to be processed, forming a recess on the film to be processed by performing a first etching process by plasma using a gas containing hydrogen fluoride, forming a first protective layer containing nitrogen, hydrogen, and fluorine by supplying a gas containing nitrogen and hydrogen to the recess without applying high frequency power, and performing a second etching process to the recess in which the first protective layer is formed thereon by the plasma.

Abstract: A semiconductor device manufacturing method according to the present embodiment includes forming a recessed part in a first insulating film. The present manufacturing method also includes forming a first conductive film containing a first metal on an inner side surface and a bottom surface of the recessed part. The present manufacturing method also includes forming an amorphous layer on the first conductive film. The present manufacturing method also includes forming a second conductive film containing the first metal on the amorphous layer.

Abstract: A film forming apparatus of embodiments includes: a chamber including a sidewall; a shower head provided in an upper part of the chamber; a holder provided in the chamber holding a substrate; a first gas supply pipe supplying a first gas to the shower head; a first valve provided in the first gas supply pipe; at least one gas supply portion provided in a region of the chamber other than the shower head; a second gas supply pipe supplying a second gas to the at least one gas supply portion; a second valve provided in the second gas supply pipe; a gas exhaust pipe exhausting a gas from the chamber; and an exhaust device connected to the gas exhaust pipe.

Abstract: A method of manufacturing a resist according to an embodiment includes obtaining a resist mixture by mixing a raw material of the resist in a mixing vessel; repeating delivering the resist mixture from a bottom of the mixing vessel to an inlet of a filter, the filter including the inlet and an outlet; filtering the resist mixture using the filter; and delivering the filtered resist mixture from the outlet to the mixing vessel; obtaining a first mixture by mixing the resist mixture and a predetermined first solution, the resist mixture being obtained from between the bottom and the inlet; measuring first defects of the first mixture; obtaining a second mixture by mixing the resist mixture and the predetermined first solution, the resist mixture being obtained from between the outlet and the mixing vessel; measuring second defects of the second mixture; and comparing the first defects and the second defects.

Abstract: According to one embodiment, a template includes a base material with a first surface at a first level. A first pattern on the template includes first protruding portions in a first region that protrude to a second level beyond the first level, a first recess portion between an adjacent pair of first protruding portions in a central portion of the first region, and a second recess portion between another adjacent pair of first protruding portions in an outer peripheral portion of the first region. A second pattern on the template includes a protrusion portion in a second region outside the first region. The protrusion portion protrudes to a third level. An optical layer is in the first recess portion and at least a portion of a bottom surface of the second recess portion is not covered by the optical layer.

Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

Abstract: A first chip includes a substrate, and first and second electrodes in a second region surrounding a first region. A second chip includes an interconnect layer, third and fourth electrodes in the second region, and first and second walls. Each of the first and third electrodes and the first wall includes a conductor surrounding the first region. The first and second electrodes are respectively in contact with the third and fourth electrodes. The first and second walls are in contact with the interconnect layer and are electrically coupled to the substrate via the first and third electrodes and the second and fourth electrodes, respectively. Each of a first ratio of an area covered by the first and second electrodes to the second region and a second ratio of an area of the third and fourth electrodes to the second region is 3% or more and 40% or less.

Abstract: According to one embodiment, a memory system comprises a non-volatile memory that includes a plurality of memory cells and a memory controller. The memory controller is configured to set a first read voltage based on a first shift value, acquire hard bit data by a first read operation using the first read voltage, set a second read voltage based on a second shift value, acquire soft bit data by a second read operation using the second read voltage, execute first error correction by using the hard bit data and the soft bit data, calculate a first log likelihood ratio (LLR) by using at least a result of the first error correction that has failed, and correct at least one of the first shift value and the second shift value based on the first LLR.

Abstract: An information processing apparatus comprises processing circuitry that acquires output data obtained by performing an experiment or simulation based on an input parameter and a physical quantity of the output data, inputs the output data to a learned model, extracts a feature amount of the output data, generates a first reference feature amount, generates a second reference feature amount based on the physical quantity of the output data and a degree of similarity between the first reference feature amount and the feature amount of the output data, calculates degree of similarity between the second reference feature amount and the feature amount of the output data, sets an evaluation value based on the calculated degree of similarity and the physical quantity of the output data, determines an input parameter for a next experiment or simulation based on the evaluation value, and repeats the above processings until a predetermined condition is satisfied.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an element region provided on the semiconductor layer convexly, having a predetermined width in a first direction along a surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction, a gate electrode arranged above the element region, a liner layer covering the gate electrode, and an element separation portion extends in the second direction on both sides of the element region in the first direction, and the liner layer continuously extends from the gate electrode to the element separation portion and the liner layer in the element separation portion lies below the element separation portion.

Abstract: According to one embodiment, a semiconductor device includes: a stacked body including an insulating layer, and a conductive layer containing molybdenum; an aluminum oxide layer provided between the insulating layer and the conductive layer; and a protective layer in contact with the aluminum oxide layer, containing one of carbon, nitrogen, or sulfur bonded to aluminum in the aluminum oxide layer, and also in contact with the conductive layer.

Abstract: A semiconductor device includes first conductive layers, a width in a first direction thereof being a first width, a second conductive layer arranged with first conductive layers, a smaller one of a width in the first direction thereof and a width in a second direction thereof being a second width that is larger than the first width, a third conductive layer in contact with one end portion of at least one of first conductive layers, and a fourth conductive layer in contact with one end portion of the second conductive layer. The at least one of first conductive layers and the second conductive layer contain a first metal, a second metal, and oxygen (O). A concentration of the first metal of the at least one of first conductive layers is higher than a concentration of the first metal of the second conductive layer.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

Abstract: According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Abstract: According to one embodiment, a semiconductor memory device includes: a first stacked body that includes a memory region, a stepped region, and a connection region arranged in a first direction; a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction; a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region in the stacking direction; and a plurality of third pillars that extends in the first stacked body in the stacking direction, and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.

Abstract: According to an embodiment, a generation method includes setting and writing. The setting is to set one of multiple first nodes as a second node. The multiple first nodes are included in a directed graph and are each assigned with an ID. The multiple first nodes respectively correspond to multiple first vectors included in a search range. The writing is to write an information piece that is an element related to the second node out of elements of index information corresponding to the directed graph. The information piece includes a second vector that is a first vector corresponding to a second node out of the multiple first vectors. The information piece includes an ID and a third vector for each of third nodes. The third nodes are all out-neighbor nodes of the second node. The third vector corresponds to one of the third nodes.

Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a push-up device, a transfer device, an electronic component holding device, and a mounting device. The push-up device is capable of pushing up a plurality of adjacent electronic components among a plurality of electronic components diced from a wafer. The transfer device is capable of transferring the plurality of electronic components pushed up by the push-up device. The electronic component holding device is capable of holding the plurality of electronic components transferred by the transfer device. At least part of the push-up device is capable of pushing up the plurality of adjacent electronic components by spanning the adjacent electronic components on the same surface. The electronic component holding device is capable of switching, for each of the electronic components, a holding state of the electronic component and a non-holding state of the electronic component.