Patents Assigned to Kioxia Corporation
  • Publication number: 20240071478
    Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Hideyuki KATAOKA, Yoshinao SUZUKI, Mai SHIMIZU, Kazuyoshi MURAOKA, Masami MASUDA, Yoshikazu HOSOMURA
  • Publication number: 20240070006
    Abstract: According to one embodiment, when a code rate is less than 1, a controller encodes a plurality of pieces of write data to generate a codeword including the plurality of pieces of write data and one or more erasure recovery codes. The controller calculates a cumulative error count. The controller calculates at least one of a cumulative write amount or a cumulative read amount. The controller change the code rate such that the code rate is increased when a first value which is obtained by dividing the cumulative error count by the cumulative write amount or the cumulative read amount is less than a first threshold value, and the code rate is decreased when the first value is larger than or equal to a second threshold value.
    Type: Application
    Filed: March 8, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Yuki SASAKI
  • Publication number: 20240068094
    Abstract: A piping includes a first pipe part having a first end connected to a processing chamber and a second end connected to another piping; a second pipe part connected to the first pipe between the first end and the second end, and configured to supply hydrogen gas or hydrogen radicals into the first pipe part; a valve provided between the second pipe part and the second end, and configured to open and close the first pipe part; and a metal film coated on an inner wall of the first pipe part.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventor: Yuya MATSUBARA
  • Publication number: 20240071499
    Abstract: An information processing device includes a string including a first transistor and a second transistor, and a first wiring line connected to an end of the string. The first transistor has a threshold voltage corresponding to first data. The second transistor has a drain and a source, and a resistance value between the drain and the source corresponds to second data. A current corresponding to a product of the first data and the second data flows through the string.
    Type: Application
    Filed: March 15, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventor: Atsushi KAWASUMI
  • Publication number: 20240074214
    Abstract: A semiconductor memory device includes a plurality of transistors arranged in a first direction, and arranged in a second direction and a first wiring layer disposed between a semiconductor substrate and a plurality of voltage supply wirings. Each of the plurality of transistors includes a source region and a drain region. The first wiring layer includes a plurality of first connecting portions disposed at positions overlapping with the plurality of source regions when viewed in a third direction and electrically connected to the plurality of source regions and the plurality of voltage supply wirings, a plurality of second connecting portions disposed at positions overlapping with the plurality of source regions when viewed in the third direction and electrically connected to a plurality of the drain regions and a plurality of conductive layers, and a passing wiring region disposed between a pair of the second connecting portions.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 29, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Nobuaki OKADA, Akihiko CHIBA, Kenichi MATOBA, Haruna SUGIURA
  • Publication number: 20240071477
    Abstract: A memory system for speeding up a read operation in the memory system includes a first pillar, a first string including a first transistor and a first memory cell, a second string including a second transistor and a second memory cell, a first bit line, a first gate line, a first word line, a second gate line, a second word line and a control circuit. When the control circuit executes a read operation with respect to the first memory cell, the control circuit is configured to apply a read voltage to the first word line, apply a voltage turning off the second memory cell regardless of an electric charge stored in the second memory cell to the second word line, apply a voltage turning on the first transistor to the first gate line, and apply a voltage turning on the second transistor to the second gate line.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazutaka IKEGAMI, Rieko FUNATSUKI, Nobuyuki MOMO, Hidehiro SHIGA
  • Publication number: 20240069430
    Abstract: An exposure mask includes a substrate having a first main surface and a second main surface, a reflective layer that is provided on the first main surface side and reflects exposure light, and an absorption layer that is provided with a predetermined pattern on the first main surface side via the reflective layer and absorbs the exposure light, in which the reflective layer includes a first region of which a surface height from the second main surface is a first height, and a second region which is adjacent to the first region via a first step on a surface of the reflective layer, and of which a surface height from the second main surface is a second height higher than the first height, and the absorption layer is provided in each of the first region and the second region.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventor: Naoki SATO
  • Publication number: 20240074327
    Abstract: According to one embodiment, a magnetic memory device includes: a first interconnect; a second interconnect; a first switching element provided on the first interconnect; a second switching element provided on the second interconnect; a first insulating layer provided surrounding the first switching element; a second insulating layer surrounding the second switching element and not being in contact with the first insulating layer; a first conductor provided on the first switching element and the first insulating layer; a second conductor provided on the second switching element and the second insulating layer; a first magnetoresistive effect element provided on the first conductor; and a second magnetoresistive effect element provided on the second conductor.
    Type: Application
    Filed: June 12, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Taichi IGARASHI, Yuichi ITO, Eiji KITAGAWA, Masayoshi IWAYAMA
  • Publication number: 20240071928
    Abstract: A semiconductor device according to the embodiment includes: a first interlayer insulating film; a lower wiring layer provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film and having a first trench provided therein; and an upper wiring layer provided in the first trench of the second interlayer insulating film and electrically connected to the lower wiring layer, wherein the upper wiring layer includes: a first barrier metal film provided in the first trench, and mainly composed of Ta; a second barrier metal film provided in the first trench via the first barrier metal film, and mainly composed of Ti; and a first conductive film provided in the first trench via the first barrier metal film and the second barrier metal film, and mainly composed of a first metal.
    Type: Application
    Filed: June 13, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventor: Akira NAKAJIMA
  • Publication number: 20240074172
    Abstract: In one embodiment, a semiconductor storage device includes a lower electrode layer, a lower insulator, an upper electrode layer and an upper insulator along a first direction. The device further includes a first insulator provided on a side of a second direction of the upper electrode layer, and a second insulator provided between the upper electrode layer and the lower/upper/first insulator. The device further includes a charge storage layer, a third insulator and a semiconductor layer sequentially provided on a side of the second direction of the first insulator. A side face of the first insulator on a side of the upper electrode layer has a convex shape, the charge storage layer includes a first portion having a first thickness, and a second portion having a second thickness less than the first thickness, and the first portion is in contact with the first insulator.
    Type: Application
    Filed: March 10, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Keiichi SAWA, Tomoyuki TAKEMOTO, Yuta KAMIYA, Hiroyuki YAMASHITA, Yuta SAITO, Tatsunori ISOGAI
  • Publication number: 20240071826
    Abstract: A position determining method according to the present embodiment is a position determining method of a wafer which has a plurality of singulated chips and which is pasted on a tape. In addition, the present position determining method includes irradiating, with light, the wafer which has a first cut mark provided between the chips and a second cut mark with a width that differs from a width of the first cut mark. Furthermore, the present position determining method includes receiving irradiated light at a position opposing an irradiation position of light across the wafer. In addition, the present position determining method includes determining a position of the wafer based on a width of received light having passed through the wafer.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventor: Takanobu ONO
  • Publication number: 20240074196
    Abstract: A memory pillar penetrates first conductors that are aligned in a first direction separately from each other. A first member penetrates the first conductors in the first direction and has a first portion and second portions. The first portion extends in a second direction intersecting with the first direction. The second portions are aligned spaced apart in the second direction on an upper surface of the first portion. A length of each second portion in a third direction intersecting with the first and second directions is shorter than a length of the first portion in the third direction. The first member further includes a bridge that is positioned on the upper surface of the first portion and between two neighboring ones of the second portions and extends on the upper surface of the first portion across both ends of the first portion.
    Type: Application
    Filed: June 12, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventor: Hiroaki NAITO
  • Patent number: 11915116
    Abstract: An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Miyashita, Shouhei Kousai
  • Patent number: 11914544
    Abstract: According to one embodiment, a memory system includes a board, a memory controller, and a semiconductor memory. When a signal input to a third port or a command received from an outside of the memory system satisfies a first condition, the memory controller is configured to use a first port as a first signal port and to use a second port as a second signal port. When the signal input to the third port or the command received from the outside of the memory system satisfies a second condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Nana Kawamoto, Naoki Kimura
  • Patent number: 11915748
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Noboru Shibata, Yasuyuki Matsuda
  • Patent number: 11917824
    Abstract: A semiconductor storage device of an embodiment includes: a plurality of columnar bodies that penetrate a predetermined film; and a beam that reaches a predetermined depth of the predetermined film shallower than depths of the plurality of columnar bodies and couples the plurality of columnar bodies together with a width smaller than widths of the plurality of columnar bodies.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventor: Takahiro Adachi
  • Patent number: 11917827
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventor: Naoki Yasuda
  • Patent number: 11917930
    Abstract: A resistance change device of an embodiment includes: a first electrode; a second electrode; and a stack disposed between these electrodes, and including a first layer containing a resistance change material and a second layer in contact with the first layer. The resistance change material contains at least one of a first element such as Ge and a second element such as Sb, and at least one third element selected from Te, Se, S, and O. The second layer contains a crystal material containing at least one selected from a group consisting of a first material having a composition represented by (Ti,Zr,Hf)CoSb, (Zr,Hf)NiSn, or Fe(Nb,Zr,Hf)(Sb,Sn), a second material having a composition represented by Fe(V,Hf,W)(Al,Si), and a third material having a composition represented by Mg(Si,Ge,Sn).
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Takao Kosaka, Hiroki Tokuhira
  • Patent number: 11917829
    Abstract: A semiconductor memory device comprises a semiconductor substrate comprising a first region, a second region, and a third region provided therebetween. The first region comprises: first conductive layers; a first semiconductor layer facing the first conductive layers; and a second semiconductor layer connected to the first semiconductor layer. The second region comprises: a third semiconductor layer and fourth semiconductor layer; and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The third region comprises a fifth semiconductor layer and sixth semiconductor layer that are formed continuously with the second semiconductor layer and the third semiconductor layer or fourth semiconductor layer, and extend in a second direction. The third region comprises first and second portions aligned alternately in the second direction.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Ayaka Takeoka, Yoshitaka Kubota
  • Patent number: 11915778
    Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Arizono, Akio Sugahara, Mitsuhiro Abe, Mitsuaki Honma