Abstract: According to one embodiment, a semiconductor storage device is provided which includes a stacked body, a first pillar portion, a first separating portion, and a first supporting post. In the stacked body, a plurality of insulating layers and a plurality of electrically conductive layers are stacked alternately one on another. The stacked body is provided on a predetermined electrically conductive film. The first pillar portion includes a plurality of memory cells, and penetrates through the stacked body in a stacking direction of the stacked body. The first separating portion separates the stacked body into a plurality of blocks. The first supporting post extends locally within the stacked body from an upper surface of the predetermined electrically conductive film in the stacking direction.

Abstract: A semiconductor memory device according to an embodiment includes a substrate. The substrate includes first and second areas, and block areas. The second area includes subareas. Each of the subareas includes a contact area and an insulating area arranged in the first direction. The contact area includes terraced portions and first contacts corresponding to two block areas. The insulating area includes second contacts corresponding to the two block areas. Contact areas of odd-numbered subareas and insulating areas of even-numbered subareas are disposed in an alternating manner in the second direction. Insulating areas of the odd-numbered subareas and contact areas of the even-numbered subareas are disposed in an alternating manner in the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor, a second memory cell transistor, and a first select element that connects the first memory cell transistor and the second memory cell transistor in series, a second memory string including a third memory cell transistor, a fourth memory cell transistor, and a second select element that connects the third memory cell transistor and the fourth memory cell transistor in series, and a control circuit. The control circuit is configured to set the second select element to an off state while setting the first select element to an on state when reading data of the first memory string.

Abstract: An analysis system includes a stage that supports a sample. The analysis system includes a first supplier configured to provide a hydrophobic material on the sample, and surround an inspection region on the sample with the hydrophobic material. The analysis system includes a second supplier configured to provide an inspection liquid over the inspection region. The analysis system includes a collector configured to collect the inspection liquid. The analysis system includes an analyzer configured to analyze a component contained in the collected inspection liquid.

Abstract: A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.

Abstract: A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.

Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

Abstract: According to one embodiment, a device includes a member including a first portion having a first dimension in first direction, a second portion spaced from the first portion and having a second dimension in the first direction, a third portion between the first and second portions and having a third dimension in the first direction, and a fourth portion between the first and third portions and having a fourth dimension in the first direction; and a circuit to supply a shift pulse including first and second pulses to the member and move a domain wall in the member. The third dimension is less than the first dimension. The second and fourth dimensions are less than the third dimension. A second value of the second pulse is less than a first value of the first pulse.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a plurality of insulating films and a plurality of electrode films provided alternately on the substrate. The semiconductor device further includes a first insulating film, a first charge storage film, a third insulating film, a second charge storage film, a second insulating film, and a first semiconductor film that are sequentially provided along at least one side surface of each of the electrode films. The first charge storage film includes either (i) molybdenum, or (ii) titanium and nitrogen, and the second charge storage film includes a semiconductor film.

Abstract: According to one embodiment, a magnetic memory device including a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and containing magnesium (Mg) and oxygen (O). The nonmagnetic layer further contains a first additive element and a second additive element, the first additive element is at least one element selected from sulfur (S), gallium (Ga), aluminum (Al), titanium (Ti), vanadium (V), hydrogen (H), fluorine (F), manganese (Mg), lithium (Li), nitrogen (N) and magnesium (Mg), and the second additive element is lithium (Li).

Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.

Abstract: According to one embodiment, a misalignment measuring apparatus includes: an input circuit; a storage medium; a first circuit configured to, in a first calibration pattern, calculate a second misalignment amount; a second circuit configured to, using a first image of a second calibration pattern, calculate a third misalignment amount; a third circuit configured to calculate a coefficient indicating; and a fourth circuit configured to, using a second image corresponding to the first and second patterns, calculate a third center position of a third contour and calculate the first misalignment amount between the first pattern and the second pattern based on the fourth misalignment amount and the coefficient.

Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

Abstract: According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.

Abstract: A semiconductor device includes: a semiconductor substrate having a first surface; a device area that is formed on the semiconductor substrate and includes a semiconductor element; and a conductive member that surrounds the device area and extends in a first direction perpendicularly intersecting the first surface. The conductive member is formed on the semiconductor substrate, and includes a first pattern and a second pattern, the second pattern overlapping the first pattern in the first direction. A pitch of the first pattern in a second direction intersecting the first direction is different from a pitch of the second pattern in the second direction.

Abstract: A storage device of an embodiment includes a first conductive layer; a second conductive layer; a fluid layer between the first conductive layer and the second conductive layer; particles in the fluid layer; a first control electrode between the first conductive layer and the second conductive layer; a first insulating layer between the first conductive layer and the first control electrode surrounding the fluid layer; and a second insulating layer between the first control electrode and the second conductive layer surrounding the fluid layer. In this storage device, a first cross-sectional area of the fluid layer in a first cross-section perpendicular to a first direction is smaller than a second cross-sectional area of the fluid layer in a second cross-section perpendicular to the first direction. The first cross-section includes the first control electrode, and the second cross-section includes the second insulating layer.

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

Abstract: In one embodiment, a semiconductor device includes a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction. The device further includes a columnar portion including a charge storage layer and a first semiconductor layer extending through the stacked film in the first direction, the first semiconductor layer including an impurity element. The device further includes a second semiconductor layer or a first insulator provided on the stacked film and the columnar portion, the second semiconductor layer or the first insulator including the impurity element and having a concentration gradient of the impurity element in the first direction.