Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

Abstract: A controller of a memory system estimates a use of each of a plurality of command queues based on types of one or more commands fetched from each of the plurality of command queues. The controller determines a command queue from which a next command is to be fetched from the plurality of command queues based on the use of each of the plurality of command queues and a usage state of a resource in the memory system. The controller fetches a command from the determined command queue.

Abstract: A semiconductor memory device includes: a substrate; a first wiring layer including a first conductive layer and a second conductive layer; a second wiring layer disposed between the substrate and the first wiring layer; and a memory cell array layer disposed between the substrate and the second wiring layer. The memory cell array layer includes: a plurality of third conductive layers arranged in a first direction intersecting with a surface of the substrate; a semiconductor layer extending in the first direction and opposed to the plurality of third conductive layers; and an electric charge accumulating layer disposed between the plurality of third conductive layers and the semiconductor layer. The second wiring layer includes: a fourth conductive layer connected to one end portion of the semiconductor layer in the first direction; and a fifth conductive layer opposed to the first conductive layer and electrically connected to the second conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.

Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.

Abstract: A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

Abstract: According to embodiments, a substrate treatment apparatus includes a housing, a heater and a pipe. The housing stores solution containing phosphoric acid and houses a substrate including a silicon substrate. The heater heats the solution over a normal boiling point of the solution. The pipe supplies heated solution heated by the heater into the housing while generating air bubbles.

Abstract: According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.

Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.

Abstract: According to one embodiment, a memory system includes a controller controls writing data to a non-volatile memory and a volatile memory, a power supply circuit generates voltages with a first voltage externally supplied and supplies the voltages to the non-volatile memory, volatile memory, and controller, and a backup power supply circuit. The power supply circuit, when the first voltage drops irrespective of a shutdown command, generates the voltages with an output voltage of the backup power supply circuit. The controller changes a size of data storable in the volatile memory in accordance with a supply capability fed from the backup power supply circuit.

Abstract: A semiconductor storage device of an embodiment includes: a laminated body including electrode layers and insulating layers alternately stacked in a first direction; a semiconductor layer disposed in the laminated body; a first insulating film disposed between the laminated body and the semiconductor layer; a charge storage film disposed between the laminated body and the first insulating film, thicknesses of the charge storage film in a second direction crossing the first direction in the regions corresponding to the electrode layers being different from that in the regions corresponding to the insulating layers, the charge storage film comprising: a second insulating film disposed between the laminated body and the first insulating film, and a third insulating film disposed between the second insulating film and the regions corresponding to the electrode layers, the third insulating film having a density different from that of the second insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a word line coupled to a gate of the first memory cell; a first transistor having a first end coupled to the word line; and a control circuit configured to, in a read operation, apply a first voltage, which is positive, to a back gate of the first transistor.

Abstract: An apparatus includes a process chamber, a stage, a shower head, a plasma generation circuit, and a partition wall. The stage places a substrate. The shower head faces the stage and supplies process gas to the substrate. The plasma generation circuit generates plasma between the shower head and the stage. The partition wall isolates a first space between the shower head and the stage from a second space on a side of the shower head opposite to a side of the stage with a predetermined first gap, such that a pressure in the second space is higher than a pressure in the first space in a state where the process gas is supplied from the shower head, a gas different from the process gas is supplied to the second space, and an inside of the first space is evacuated.

Abstract: A memory system for low power consumption and high speed read operation in the memory system includes a source line, a string select line having i layers, a first word line having i layers, a second word line having i layers, a select gate line having 1 layer which is divided into 2n, a plurality of memory pillars and a control circuit. Each of the plurality of memory pillars includes a first string and a second string. The first string includes a first transistor, i first memory cells and j second memory cells. The first transistor, the i first memory cells, and the j second memory cells are electrically connected in series. The second string includes a second transistor, i third memory cells, and j fourth memory cells. The second transistor, the i third memory cells, and the j fourth memory cells are electrically connected in series.

Abstract: A semiconductor memory device according to the present disclosure includes a memory cell array (110, 210), an input/output circuit (23) that inputs/outputs a signal from/to the memory cell array, and a temperature acquiring circuit (29) that generates temperature information according to the temperature of the memory cell array, and corrects the characteristics of the input/output circuit based on the temperature information.