Patents Assigned to Kioxia Corporation
  • Publication number: 20230033947
    Abstract: A memory system comprising a first storage region which stores first firmware corresponding to an external first electronic control apparatus; a second storage region which stores second firmware corresponding to an external gateway and third firmware corresponding to the first electronic control apparatus; and a controller configured to transmit the second firmware and the third firmware to the gateway on the basis of a first command received from the gateway, and transmit the first firmware to the gateway on the basis of a second command received from the gateway.
    Type: Application
    Filed: October 4, 2022
    Publication date: February 2, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Atsushi YAMAZAKI, Kentaro UMESAWA, Naoko YAMADA, Yuta KAGEYAMA
  • Publication number: 20230030470
    Abstract: According to one embodiment, a substrate supporting apparatus includes a mounting plate that is configured by including ceramics and has a mounting surface on which the substrate is to be mounted; a power supply plate that is built in the mounting plate and electrostatically attracts the substrate to the mounting plate; a plurality of protruding portions which internally includes an electrically conductive member respectively, is arranged on at least a central region and outer edge region of the mounting plate, and protrudes from the mounting surface; and a plurality of elastic members which is embedded in the mounting plate to correspond to the plurality of protruding portions, supports the plurality of protruding portions while protruding the protruding portions from the mounting surface, and electrically connects the power supply plate and the electrically conductive members included in the plurality of protruding portions to each other.
    Type: Application
    Filed: December 8, 2021
    Publication date: February 2, 2023
    Applicant: Kioxia Corporation
    Inventor: Ryo SHINOZAKI
  • Publication number: 20230031132
    Abstract: A semiconductor device according to an embodiment includes a plurality of conductive layers stacked apart from each other and extending in a plate shape in a direction crossing a stacking direction; a channel body including a semiconductor film and penetrating the plurality of conductive layers; a memory film including a charge accumulation film and provided between the plurality of conductive layers and the channel body; and a high dielectric constant (high-k) film arranged between the plurality of conductive layers and the memory film while being divided in a circumferential direction surrounding the memory film.
    Type: Application
    Filed: December 17, 2021
    Publication date: February 2, 2023
    Applicant: Kioxia Corporation
    Inventor: Muneyuki TSUDA
  • Publication number: 20230030121
    Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.
    Type: Application
    Filed: October 12, 2022
    Publication date: February 2, 2023
    Applicant: Kioxia Corporation
    Inventors: Akifumi GAWASE, Atsuko SAKATA
  • Publication number: 20230032616
    Abstract: A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Applicant: Kioxia Corporation
    Inventor: Yoshiaki ASAO
  • Publication number: 20230031541
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 2, 2023
    Applicant: Kioxia Corporation
    Inventor: Hiroyuki NAGASHIMA
  • Patent number: 11569253
    Abstract: A semiconductor memory device includes multiple first electrode layers stacked in a first direction, multiple second electrode layers stacked in the first direction, a first columnar body extending through the multiple first electrode layers in the first direction, a second columnar body extending through the multiple second electrode layers in the first direction, a connection part connecting the first columnar body and the second columnar body, and a spacer film having an island configuration surrounding the connection part. The multiple first electrode layers and the multiple second electrode layers are arranged in the first direction, and the connection part and the spacer film are provided between the multiple first electrode layers and the multiple second electrode layers.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Takeshi Nagatomo, Tatsuo Izumi, Ryota Suzuki, Takuya Nishikawa, Yasuhito Nakajima, Daiki Takayama, Hiroaki Naito, Genki Kawaguchi
  • Patent number: 11568936
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 11569256
    Abstract: A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Kiyomi Naruke, Shinichiro Shiratake, Mutsumi Okajima, Hidetoshi Saito, Hirofumi Inoue
  • Patent number: 11568074
    Abstract: According to one embodiment, a memory system is connectable to a host including a first volatile memory and includes a non-volatile memory and a controller. The controller may use a first area of the first volatile memory as a temporary storage memory of data stored in the non-volatile memory and controls the non-volatile memory. The controller generates a first parity by using first data stored in the non-volatile memory and a key value to store the first data and the generated first parity in the first area. In the case of reading the first data stored in the first area, the controller reads the first data and the first parity to verify the read first data using the read first parity and the key value.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Keigo Hara
  • Patent number: 11569241
    Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer. The oxide semiconductor layer includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region in which at least one anion element selected from the group consisting of fluorine and chlorine is contained within a range of 1 atomic % or more and less than 8 atomic % in the metal oxide.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Hiroki Kawai, Junji Kataoka, Keiji Ikeda
  • Patent number: 11568939
    Abstract: A semiconductor storage device includes a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier that reads data from the memory cell transistor via the bit line. During an operation of determining first data and second data, while continuously applying a first voltage to a gate of the memory cell transistor, the sense amplifier first determines the first data based upon a second voltage, and then determines the second data based upon a third voltage lower than the second voltage.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventor: Mario Sako
  • Patent number: 11567830
    Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yuma Yoshinaga, Tomoya Kodama, Osamu Torii, Kenichiro Furuta, Ryota Yoshizawa
  • Patent number: 11569977
    Abstract: A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Shoun Matsunaga
  • Patent number: 11569061
    Abstract: A multibeam scanning apparatus of an embodiment is a multibeam scanning apparatus configured to emit a plurality of electron beams to a plurality of scan regions set in a matrix on an object and obtain an observation image by detecting secondary beams, the apparatus including a control circuit. Each of the scan regions includes a plurality of separated scan regions obtained by separating the each of the scan regions in a direction orthogonal to a scanning direction of the electron beams. The control circuit controls the irradiation positions of the electron beams, in two of the scan regions adjacent to each other in the scanning direction of the electron beams, such that the separated scan regions to be scanned at a same time are displaced from each other by a predetermined distance in the direction orthogonal to the scanning direction of the electron beams.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventor: Osamu Nagano
  • Patent number: 11568901
    Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Kazushige Kawasaki, Masayuki Miura, Hideko Mukaida
  • Patent number: 11568910
    Abstract: According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Naomi Takeda, Masanobu Shirakawa
  • Patent number: 11568935
    Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi, Kensuke Yamamoto, Masato Dome, Kei Shiraishi, Junya Matsuno, Kenro Kubota
  • Publication number: 20230022082
    Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.
    Type: Application
    Filed: June 15, 2022
    Publication date: January 26, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Zhao LU, Yuji NAGAI, Akio SUGAHARA, Takehisa KUROSAWA, Masaru KOYANAGI
  • Publication number: 20230023327
    Abstract: A semiconductor storage device according to an embodiment includes a substrate, a first word line, a second word line, a first channel, a first memory film, a second channel, a second memory film, a first insulating layer, a first source line, and a first drain line. The second word line is separated from the first word line in a second direction. The first channel is aligned with the first word line in a third direction. The second channel is aligned with the second word line in the third direction. The first insulating layer is positioned between the first word line and the second word line in the second direction and between the first channel and the second channel in the second direction. The first source line and first drain line extend in the second direction.
    Type: Application
    Filed: June 15, 2022
    Publication date: January 26, 2023
    Applicant: Kioxia Corporation
    Inventors: Satoshi NAGASHIMA, Yefei HAN