Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: According to One embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.

Abstract: A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Abstract: A semiconductor storage device includes a first memory chip having a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit, and a second memory chip having a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit. During a read operation executed in the first memory chip, the first, second, and fourth voltage step-up circuits supply a first voltage to the first word line, and when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.

Abstract: A semiconductor device includes a substrate. A gate insulating film is formed on the surface of the substrate. A first gate electrode layer is formed on the gate insulating film. A second gate electrode layer is formed on the first gate electrode layer and electrically connected to the first gate electrode layer. A first contact extends through the second gate electrode layer to reach the first gate electrode layer. First and second impurity layers are formed on opposite sides of the first and second gate electrode layers.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including a non-volatile storage including a superblock and a controller configured to notify a host of a size of the superblock to a host, determine a stream that aligns with the superblock, write data corresponding to the stream to the superblock, and determine that writing the data correspond to the stream has completed.

Abstract: A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.

Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

Abstract: According to one embodiment, a memory system includes nonvolatile memory including a plurality of memory areas and a memory controller. A read operation includes a first operation of reading data from a memory cell array and a second operation of transmitting at least a part of the read data to the memory controller. The memory controller determines, when executing the read operation in a first memory area and a second memory area in parallel, priorities of the second operation in the first memory area and the second operation in the second memory area based on a result of comparison between (A) a first total time period of the read operation in the first memory area and (B) a second total time of the read operation in the second memory area.

Abstract: A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

Abstract: A semiconductor device includes a conductive film containing molybdenum and a metal element. The metal element has a melting point lower than the melting point of molybdenum and forms a complete solid solution with molybdenum. The metal element as a material for composing the conductive film is at least one selected from the group consisting of, for example, titanium, vanadium, and niobium.

Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: A semiconductor device according to an embodiment includes: a logic control circuit to which a signal is input; a timing information storage circuit configured to store timing information related to a start timing of correction processing that corrects a duty cycle of the signal; and a sequencer configured to start execution of the correction processing based on the timing information when a command related to the execution of the correction processing is received.

Abstract: A memory cell is coupled between first and interconnects and includes a variable resistance element and a switching element. The variable resistance element includes first and second ferromagnetic layers and an insulating layer between the first and second ferromagnetic layers. A first circuit is configured to apply a first voltage to the first interconnect. A second circuit is configured to apply a second voltage to the second interconnect. A third circuit is configured to apply a third voltage to the second interconnect. A fourth circuit is configured to apply a fourth voltage to the first interconnect. A sense amplifier circuit is coupled to the first and second interconnects.

Abstract: A certain embodiment includes: first wiring layers extended in a first direction and arranged in a second direction; second wiring layers provided above the first wiring layer of a third direction and arranged in the first direction and extended in the second direction; first stacked structures comprising a first memory cell disposed between the second and first wiring layers at a crossing portion between the second and first wiring layers; first conductive layers provided in the same layer as the first wiring layers, adjacent to the first wiring layer in the second direction, and not connected to other than the second wiring layer; second stacked structures disposed at crossing portions between the second wiring layers and the first conductive layers; and an insulation layer provided between the first stacked structures and between the second stacked structures having a Young's modulus larger than that of the insulation layer.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.