Abstract: Methods of precisely analyzing and modeling band gap energies and electrical properties of a thin film are provided. One method includes: obtaining a substrate and a thin film disposed above the substrate, the thin film including an interfacial layer above the substrate, and a high-k layer above the interfacial layer; determining a thickness of the thin film; analyzing the thin film using deep ultraviolet spectroscopy ellipsometry to determine the photon energy of reflected light; using a model to determine a set of bandgap energies extracted from a set of results of the photon energy of the analyzing step; and determining at least one of: a leakage current from a main bandgap energy, a nitrogen content from a sub bandgap energy, and an equivalent oxide thickness from the nitrogen content and a composition of the interfacial layer.

Abstract: Disclosed is an apparatus for analyzing a plurality of image portions of at least a region of a sample. The apparatus includes a plurality of processors arranged to receive and analyze at least one of the image portions, and the processors being arranged to operate in parallel. The apparatus also includes a data distribution system arranged to receive image data, select at least a first processor for receiving a first image from the image data, select at least a second processor for receiving a second image from the image data, and output the first and second image portions to their selected processors.

Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.

Abstract: Disclosed is an optical inspection system for inspecting the surface of a substrate. The optical inspection system includes a light source for emitting an incident light beam along an optical axis and a first set of optical elements arranged for separating the incident light beam into a plurality of light beams, directing the plurality of light beams to intersect with the surface of the substrate, and focusing the plurality of light beams to a plurality of scanning spots on the surface of the substrate. The inspection system further includes a light detector arrangement including individual light detectors that correspond to individual ones of a plurality of reflected or transmitted light beams caused by the intersection of the plurality of light beams with the surface of the substrate. The light detectors are arranged for sensing the light intensity of either the reflected or transmitted light.

Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.

Abstract: Disclosed is an apparatus for analyzing a plurality of image portions of at least a region of a sample. The apparatus includes a plurality of processors arranged to receive and analyze at least one of the image portions, and the processors being arranged to operate in parallel. The apparatus also includes a data distribution system arranged to receive image data, select at least a first processor for receiving a first image from the image data, select at least a second processor for receiving a second image from the image data, and output the first and second image portions to their selected processors.

Abstract: Disclosed is an apparatus for analyzing a plurality of image portions of at least a region of a sample. The apparatus includes a plurality of processors arranged to receive and analyze at least one of the image portions, and the processors being arranged to operate in parallel. The apparatus also includes a data distribution system arranged to receive image data, select at least a first processor for receiving a first image from the image data, select at least a second processor for receiving a second image from the image data, and output the first and second image portions to their selected processors.

Abstract: A mark comprising at least one set of calibration periodic structures and at least two sets of test periodic structures, both types of which are positioned along an axis. The mark is used to measure the relative position between two layers of a device. Each set of test periodic structures has its periodic structures formed within first and second sections. The periodic structures of the first and second sections are each formed on one of the two layers of the device, respectively. The first and second sections of each test set is positioned proximate to the second and first sections of the next test set, respectively. This mark allows two beams which scan the mark to travel over both a test section formed on one layer of the device and a test section formed on the other of the two layers. Scanning multiple test sets provides multiple registration error values which are then averaged to obtain an average registration error value.

Abstract: Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity.

Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

Abstract: Disclosed is a system for detecting anomalies associated with a sample. The system includes an objective arranged proximate to a sample while the sample is undergoing chemical mechanical polishing and a beam source arranged to generate an incident beam and direct the incident beam through the objective and toward the sample while the sample is undergoing chemical mechanical polishing. The system also includes a sensor arranged to detect a scattered beam reflected from at least one anomaly associated with the sample while the sample is undergoing chemical mechanical polishing, the scattered beam being in response to the incident beam. The scattered beam indicates a characteristic of the anomaly, such as particle size.

Abstract: Disclosed is a method and apparatus for generating an image from a sample. The apparatus includes a charged particle beam generator arranged to generate and control a charged particle beam substantially towards a portion of the sample and a detector arranged to detect charged particles originating from the sample portion to allow generation of an image from the detected charged particles. The apparatus further includes a measurement device arranged to measure a characteristic of the sample portion to obtain a surface voltage value of the sample portion that is exposed to the charged particle beam. For example, the measurement device is an electrostatic voltmeter positioned to obtain a surface voltage value of the exposed sample portion. A charged particle beam is directed substantially towards a portion of the sample under a first set of operating conditions. A surface charge value of the sample portion is obtained under the first set of operating conditions.

Abstract: Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed.

Abstract: Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.

Abstract: Disclosed is a self-clearing objective for directing a beam towards a sample and clearing away debris from an optical viewing path adjacent to the sample. The self-clearing objective includes an optical element and a substantially transparent fluid flowing between the optical element and the sample such that at least a portion adjacent to the sample is substantially cleared of debris. The optical element and the fluid cooperatively direct the beam towards the sample. This self-clearing objective may be coupled with various measurement devices to measure various characteristics of samples having debris that prevents clear optical measurements. Additionally, the measurement device may be integrated with or coupled to various sample processing systems so that the relevant process may be clearly monitored.

Abstract: Disclosed is an apparatus for inspecting a sample. The apparatus includes a first electron beam generator arranged to direct a first electron beam having a first range of energy levels toward a first area of the sample and a second electron beam generator arranged to direct a second electron beam having a second range of energy levels toward a second area of the sample. The second area of the sample at least partly overlaps with the first area, and the second range of energy levels are different from the first range such that charge build up caused by the first electron beam is controlled.

Abstract: Disclosed are methods and apparatus for generating a test recipe for a metrology tool is disclosed. A plurality of first reference images that are designed to be used to fabricate a plurality of structures on a sample are provided. Each structure is imageable to form a plurality of target image patterns. A test recipe for use by a metrology tool in locating the structures on the sample is generated or modified. Generating or modifying the test recipe includes forming a plurality of second references images from the first reference images and associating the second reference images with the test recipe. The second reference images are formed to at least partially simulate one or more process effect(s) associated with fabricating the structures of the sample. Additionally, the second reference images may also be formed to simulate one or more imaging effects.

Abstract: A sample is inspected. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.