Abstract: A method for inspecting a surface of a workpiece for asymmetric defects, by scanning an incident beam on the surface of the workpiece to impinge thereon to create reflected light extending along a light channel axis in a front quartersphere and scattered light, the incident beam and the light channel axis defining an incident plane, collecting the scattered light at a plurality of collectors disposed above the surface at defined locations such that scatter from asymmetric defects is collectable by at least one collector, detecting collector output and generating signals in response, and processing the signals associated with each collector individually to obtain information about asymmetric defects.

Abstract: Provided are novel methods and systems for inspecting photomasks to identify lithographically significant contamination defects. Inspection may be performed without a separate reference image provided from a database or another die. Inspection techniques described herein involve capturing one or more test images of a photomask and constructing corresponding test “simulation” images using specific lithographic and/or resist models. These test simulation images simulate printable and/or resist patterns of the inspected photomask. Furthermore, the initial test images are used in parallel operations to generate “synthetic” images. These images represent a defect-free photomask pattern. The synthetic images are then used for generating reference simulation images, which are similar to the test simulation images but are free from lithographically significant contamination defects.

Abstract: Methods and apparatus are presented to measure the photoluminescence of incoming wafers and extract parameters such as minority carrier life time, diffusion length, and defect density that may be used to predict final solar cell efficiency. In some examples, illumination light is supplied to a side of an as-cut silicon wafer and the induced luminescence measured from the same side and the opposite side of the wafer is used to determine an indication of the minority carrier lifetime. In another example, the luminescence induced by two instances of illumination light of different wavelength is used to determine an indication of the minority carrier lifetime. In another example, the spatial distribution of luminescence intensity over an area surrounding a focused illumination spot is used to determine an indication of the minority carrier lifetime. Other apparatus useful to passivate the surface of a wafer for inspection are also presented.

Abstract: A thermally insulated electronic component package and an instrument suitable for process conditions in a high temperature environment are disclosed. The component package includes a thin electronic component, a thermally insulating outer enclosure, and an insert made of a thermally insulating material that is sized and shaped to fit within the outer enclosure. The insert includes an inner cavity sized and shaped to receive the thin electronic component. In the instrument, the outer enclosure can be configured to mount to a substrate.

Abstract: The disclosure is directed to a system and method for inspecting a sample by illuminating the sample at a plurality of different angles and independently processing the resulting image streams. Illumination is directed through a plurality of pupil apertures to a plurality of respective field apertures so that the sample is imaged by portions of illumination directed at different angles. The corresponding portions of light reflected, scattered, or radiated from the surface of the sample are independently processed. Information associated with the independently processed portions of illumination is utilized to determine a location of at least one defect of the sample. Independently processing multiple image streams associated with different illumination angles allows for retention of frequency content that would otherwise be lost by averaging information from multiple imaging angles.

Abstract: The present invention may include segmenting an image at a first resolution level and a second resolution level, wherein one or more parameters of a segmentation algorithm are trainable via user classification feedback, extracting features from a first plurality of segment primitives and a second plurality of segment primitives, wherein one or more parameters of a segment feature extraction algorithm are trainable via user classification feedback, building a first and second segmentation hierarchy by generating one or more clusters of the first plurality of segment primitives and the second plurality of segment primitives, extracting one or more features from the first segmentation hierarchy and the second segmentation hierarchy utilizing a hierarchy feature extraction algorithm, determining an inter-level relationship between the clusters generated for the first resolution level and the second level, and automatically classifying one or more tissue elements of the tissue specimen via a user-trained classific

Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.

Abstract: Photoelectron emission mapping systems for use with EUV (extreme ultraviolet) mask inspection and lithography systems are described. The mapping systems may be used to provide photoelectron emission maps for EUV photolithography masks and/or EUV mirrors. The systems use EUV photoelectron sources used for mask inspection or photolithography to impinge EUV light on the masks and/or mirrors. The EUV light generates photoelectron on the surfaces of the mask and/or mirrors and the photoelectrons are collected and analyzed by detectors placed away from optical spaces of the EUV chamber.

Abstract: Improved laser systems and associated techniques generate an ultra-violet (UV) wavelength of approximately 193.368 nm from a fundamental vacuum wavelength near 1064 nm. Preferred embodiments separate out an unconsumed portion of an input wavelength to at least one stage and redirect that unconsumed portion for use in another stage. The improved laser systems and associated techniques result in less expensive, longer life lasers than those currently being used in the industry. These laser systems can be constructed with readily-available, relatively inexpensive components.

Abstract: Systems and methods for debris mitigation in an EUV light source for semiconductor processes are disclosed. Pulsed DC electric fields are applied to the path of EUV light to reject ions from the EUV path. The pulsed DC fields are triggered to coincide with the presence of debris in the EUV optical path. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed herein is a method to enhance detection and quantification of features in the wafer edge/wafer roll off regions. Modifications and improvements have been made to earlier methods which enable improved accuracy and increased scope of feature detection.

Abstract: Various embodiments for substrate inspection are provided.

Abstract: A processor based method for measuring dimensional properties of a photoresist profile. A number acid generators and quenchers within a photoresist volume is determined. A number of photons absorbed by the photoresist volume is determined. A number of the acid generators converted to acid is determined. A number of acid and quencher reactions within the photoresist volume is determined. A development of the photoresist volume is calculated. The processor is used to produce a three-dimensional simulated scanning electron microscope image of the photoresist profile created by the development of the photoresist volume. The dimensional properties of the photoresist profile are measured.

Abstract: An optimized measurement model is determined based a model of parameter variations across a semiconductor wafer. A global, cross-wafer model characterizes a structural parameter as a function of location on the wafer. A measurement model is optimized by constraining the measurement model with the cross-wafer model of process variations. In some examples, the cross-wafer model is itself a parameterized model. However, the cross-wafer model characterizes the values of a structural parameter at any location on the wafer with far fewer parameters than a measurement model that treats the structural parameter as unknown at every location. In some examples, the cross-wafer model gives rise to constraints among unknown structural parameter values based on location on the wafer. In one example, the cross-wafer model relates the values of structural parameters associated with groups of measurement sites based on their location on the wafer.

Abstract: Systems and methods for providing micro defect inspection capabilities for optical systems such as wafer metrology tools and interferometer systems are disclosed. The systems and methods in accordance with the present disclosure may detect, classify and quantify wafer surface features, wherein the detected defects are classified and the important defect metrology information of height/depth, area and volume is reported. The systems and methods in accordance with the present disclosure therefore provide more values for quantifying the negative effect of these defects on the wafer quality.

Abstract: The present invention may include measuring a first phase distribution across a pupil plane of a portion of illumination reflected from a first overlay target of a semiconductor wafer, wherein the first overlay target is fabricated to have a first intentional overlay, measuring a second phase distribution across the pupil plane of a portion of illumination reflected from a second overlay target, wherein the second overlay target is fabricated to have a second intentional overlay in a direction opposite to and having the same magnitude as the first intentional overlay, determining a first phase tilt associated with a sum of the first and second phase distributions, determining a second phase tilt associated with a difference between the first and second phase distributions, calibrating a set of phase tilt data, and determining a test overlay value associated with the first and second overlay target.

Abstract: An adjustable, composite polarizer can include first and second plate polarizers and an adjusting apparatus. The adjusting apparatus can adjust a pitch angle and a roll angle for the first and second plate polarizers while maintaining a predetermined, minimal distance between those plates. In this configuration, the adjustable, composite polarizer can provide mirror symmetric polarization with respect to an incident plane while providing the flexibility of any polarization.

Abstract: An apparatus includes a dedicated material handling module having a dedicated automated material handling system (AMHS) defines a transport route between a first tool and a second tool selected from a plurality of tools in a fabrication facility. The dedicated ANHS is configured to transport wafer carriers between the first tool and the second tool or vice versa independent of a fabrication facility AMHS that is configured to transport wafer carriers among the plurality of tools. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis.

Abstract: The disclosure is directed to designing and using an overlay target with orthogonal underlayer dummyfill. According to various embodiments, an overlay target may include one or more segmented overlay pattern elements forming at least one overlay target structure. The overlay target may further include one or more inactive pattern elements forming at least one dummyfill target structure. Each of the one or more inactive pattern elements may include dummyfill segmented along an axis orthogonal to a segmentation axis of at least one proximately disposed overlay pattern element. In some embodiments, each of the target structures or layers may be formed from a separate process layer successively disposed upon a substrate, such as a silicon wafer. In some embodiments, the overlay and dummyfill target structures may be twofold or fourfold rotationally symmetric to allow for certain manufacturing or metrology advantages.