Patents Assigned to Kochi Industrial Promotion Center
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Patent number: 8307782Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a cooling part for cooling the processing object, wherein between the processing object and the cooling part, as compared with a thermal resistance between a central part of the processing object and the cooling part, a thermal resistance between a peripheral part peripheral to the central part and the cooling part is small.Type: GrantFiled: December 23, 2008Date of Patent: November 13, 2012Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Patent number: 8035291Abstract: An electron emission film having a pattern of diamond in X-ray diffraction and formed of a plurality of diamond fine grains having a grain diameter of 5 nm to 10 nm is formed on a substrate. The electron emission film can restrict the field intensity to a low level when it causes an emission current to flow, and has a uniform electron emission characteristic.Type: GrantFiled: May 13, 2010Date of Patent: October 11, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Patent number: 7993964Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.Type: GrantFiled: July 27, 2009Date of Patent: August 9, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Patent number: 7981734Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.Type: GrantFiled: July 8, 2009Date of Patent: July 19, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
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Patent number: 7977169Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.Type: GrantFiled: February 9, 2007Date of Patent: July 12, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu
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Patent number: 7935548Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.Type: GrantFiled: December 15, 2008Date of Patent: May 3, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Patent number: 7907700Abstract: The present invention aims to suppress calorific value and prolong a lifetime of an apparatus that generates soft X-rays. Thus, the present invention provides a static elimination apparatus that includes an emitter as an electron emitting portion and a target, in which a thin film formed of diamond particles each having a particle size of 2 nm to 100 nm is formed on a surface of the emitter. The thin film has a diamond XRD pattern in an XRD measurement and, in a Raman spectroscopic measurement, a ratio of an sp3 bonding component to an sp2 bonding component within the film of 2.5 to 2.7:1. When a DC voltage is applied to the emitter, with a threshold electric field intensity of 1 V/?m or less, electrons larger in number than the prior art are emitted from the emitter and moreover, a temperature of the emitter is hardly increased, thus obtaining a longer lifetime.Type: GrantFiled: April 10, 2007Date of Patent: March 15, 2011Assignees: Casio Computer Co., Ltd., Kochi Industrial Promotion CenterInventors: Hitoshi Inaba, Yoshinori Okubo, Yoshiyuki Yagi, Shunichi Sato, Kazuhito Nishimura
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Patent number: 7812512Abstract: A method of manufacturing a field emission electrode includes humidification processing to absorb water at a surface of an electron emission film emitting electrons as a result of application of a voltage, and voltage application processing to apply an aging voltage between the humidified electron emission film and an electrode provided facing the electron emission film.Type: GrantFiled: September 26, 2008Date of Patent: October 12, 2010Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Publication number: 20100219744Abstract: An electron emission film having a pattern of diamond in X-ray diffraction and formed of a plurality of diamond fine grains having a grain diameter of 5 nm to 10 nm is formed on a substrate. The electron emission film can restrict the field intensity to a low level when it causes an emission current to flow, and has a uniform electron emission characteristic.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito NISHIMURA, Hideki Sasaoka
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Patent number: 7755271Abstract: An electron emission film having a pattern of diamond in X-ray diffraction and formed of a plurality of diamond fine grains having a grain diameter of 5 nm to 10 nm is formed on a substrate. The electron emission film can restrict the field intensity to a low level when it causes an emission current to flow, and has a uniform electron emission characteristic.Type: GrantFiled: November 28, 2005Date of Patent: July 13, 2010Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Publication number: 20090286351Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi HIRAO, Takahiro HIRAMATSU, Mamoru FURUTA, Hiroshi FURUTA, Tokiyoshi MATSUDA
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Publication number: 20090269881Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.Type: ApplicationFiled: July 8, 2009Publication date: October 29, 2009Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru FURUTA, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
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Patent number: 7598520Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.Type: GrantFiled: June 1, 2007Date of Patent: October 6, 2009Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Thin film transistor including low resistance conductive thin films and manufacturing method thereof
Patent number: 7576394Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.Type: GrantFiled: February 1, 2007Date of Patent: August 18, 2009Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida -
Publication number: 20090169769Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a cooling part for cooling the processing object, wherein between the processing object and the cooling part, as compared with a thermal resistance between a central part of the processing object and the cooling part, a thermal resistance between a peripheral part peripheral to the central part and the cooling part is small.Type: ApplicationFiled: December 23, 2008Publication date: July 2, 2009Applicants: Kochi Industrial Promotion Center, CASIO COMPUTER CO., LTD.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Publication number: 20090155934Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.Type: ApplicationFiled: December 15, 2008Publication date: June 18, 2009Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito NISHIMURA, Hideki SASAOKA
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Publication number: 20080226838Abstract: A plasma CVD apparatus includes a first electrode which is disposed in a reacting furnace and on which a substrate is mounted, a second electrode that is disposed above and opposite the first electrode and generates plasma with the first electrode, and a first gas supply nozzle that is disposed at a height between a height of the first electrode in the reacting furnace and a height of the second electrode, and has a plurality of ejection ports formed and arranged in such a way as to surround an area between the first electrode and the second electrode where plasma is generated.Type: ApplicationFiled: December 21, 2007Publication date: September 18, 2008Applicants: KOCHI INDUSTRIAL PROMOTION CENTER, CASIO COMPUTER CO., LTD.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Publication number: 20070278490Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.Type: ApplicationFiled: June 1, 2007Publication date: December 6, 2007Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Publication number: 20070187678Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.Type: ApplicationFiled: February 9, 2007Publication date: August 16, 2007Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu
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Thin film transistor including low resistance conductive thin films and manufacturing method thereof
Publication number: 20070187760Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.Type: ApplicationFiled: February 1, 2007Publication date: August 16, 2007Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida