Abstract: Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Abstract: Methods and systems are described for reduction of crosstalk in multi-wire communications systems using ensemble codes. Constraints applied to code construction and/or permissible encoding sequences eliminate transmit patterns shown to generate capacitively coupled and/or inductively coupled crosstalk.

Abstract: Methods and systems are described for receiving a set of input bits at a plurality of drivers and responsively generating an ensemble of signals, each respective signal of the ensemble of signals generated by receiving a subset of input bits at a respective driver connected to a respective wire of a multi-wire bus, the received subset of bits corresponding to sub-channels associated with the respective wire, generating a plurality of weighted analog signal components, each weighted analog signal component (i) having a corresponding weight and sign selected from a set of wire-specific sub-channel weights associated with the respective wire and (ii) modulated by a corresponding bit of the received subset of bits, and generating the respective signal by forming a summation of the plurality of weighted analog signal components at a common node connected to the respective wire for transmission over the respective wire of the multi-wire bus.

Abstract: A management method and system of an electronic transaction between an account of a purchaser subject and an account of a seller subject is provided. The method and system allow buyers to not employ physical supports of money such as banknotes/coins, credit cards or phone devices and of carrying out payments in a dematerialized fashion. Security of payments is ensured by user's authentication, based on the recognition of at least a user's biometric parameter previously recorded in the system, by a PIN code, by the picture of the user's face and by an algorithm that identifies buying habits. An account is associated to the registered user, from which the amount to be given for the payment is debited.

Abstract: Methods and systems are described for receiving a control step input at a binary-to-thermometer decoder and responsively generating bits of a thermometer codeword representative of the control step input, providing the bits of the thermometer codeword to a plurality of differential pairs comprising a first transistor and a second transistor, each differential pair configurable for one of directing current to an in-phase (I) common node or directing current to a quadrature phase (Q) common node and switching between directing current to the I common node and the Q common node, and forming an output signal based on current drawn through the I and Q common nodes, the output signal having an intermediate phase with respect to a first and a second reference signal.

Abstract: Systems and methods for an Enhanced High Bandwidth Memory (EHBM) are described, utilizing fewer physical wires than a HBM interface with each wire operating at a much higher signaling rate. The same logical signals and commands of HBM are supported over this higher-speed transport, with the resulting lower wire count and reduced signal density allowing use of lower-cost interconnection such as an organic rather than a silicon interposer between GPU and DRAM stack.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Abstract: A device for the induction heating of a billet of metal of high electrical conductivity has: a tubular body supporting a plurality of permanent magnets arranged inside the tubular body, angularly spaced apart from each other and arranged so as to be alternated with opposite polarities. The device also has a support for the billet that is arranged inside the tubular body and faces the magnets. The device also has a motor adapted to rotate the tubular body with respect to the billet in order to induce currents in the billet that circulate within the metal material, obtaining the heating of the billet by the Joule effect. An integral cooling system for the permanent magnets is provided, this being carried by the tubular body and suitable for feeding cooling air flows between adjacent permanent magnets.

Abstract: An automatic apparatus for heating and frothing milk comprises a device for generating steam for heating the milk, a first high temperature hydraulic circuit, a refrigerating group for maintaining the conservation temperature of the milk, and a second low temperature hydraulic circuit. The refrigerating group includes a milk container and pump for drawing milk therefrom. A first total separation valve separates the second hydraulic circuit from the first hydraulic circuit, a second total separation valve modulates the quantity of air drawn by the pump, a third total separation valve separates both the first hydraulic circuit and the second hydraulic circuit from a milk dispensing circuit, a steam injection device mixes the steam with the frothed milk, and a fourth total separation valve modulates the quantity of steam outlet from the steam generating device. Each total separation valve is provided with an actuator element manufactured with a shape memory alloy.

Abstract: Tissue expanders and methods of their manufacture and use are disclosed herein. A tissue expander shell according to the present disclosure may include a shape and topography that facilitates uniform or substantially uniform expansion and contraction of the tissue expander. In at least one example, the shell may include a series of topographical features, such as ridges, grooves, channels, valleys, canals, protrusions, pleats, creases, or folds. In some embodiments, these features may have a curved or wavy cross sectional profile. For example, the shell may include a series of concentric curved ridges.

Abstract: Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.

Abstract: A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Abstract: Properties and the construction method of Orthogonal Differential Vector Signaling Codes are disclosed which are tolerant of order-reversal, as may occur when physical routing of communications channel wires causes the bus signal order to be reversed. Operation using the described codes with such bus-reversed signals can avoid complete logical or physical re-ordering of received signals or other significant duplication of receiver resources.

Abstract: A driver for transmitting multi-level signals on a multi-wire bus is described that includes at least one current source connected to a transmission line, each current source selectively enabled to source current to the transmission line to drive a line voltage above a termination voltage of a termination voltage source connected to the transmission line via a termination impedance element, wherein each of the at least one current sources has an output impedance different than a characteristic impedance of the transmission line, and at least one current sink connected to the transmission line, each current sink selectively enabled to sink current from the transmission line to drive a line voltage below the termination voltage, each of the at least one current sinks having an output impedance different than the characteristic impedance of the transmission line.

Abstract: The present invention relates to a method for improving sleep quality, comprising the steps of measuring pressure by means of sensors in locations distributed by regions of a mattress; calculating the SQI based on the prominent movements detected depending on the time of night; calculating the mean pressure measured by each sensor; calculating the difference between the mean pressure and the pressure measured by that sensor when there is no user on the mattress; calculating the mean pressure difference for each region of the mattress; calculating a weight factor for each region of the mattress; comparing the weight factor with a reference value; varying the configuration of the mattress by increasing or reducing the support level in the regions. The present invention also relates to a related system and mattress.

Abstract: Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

Abstract: Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

Abstract: Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.