Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication, The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.

Abstract: A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

Abstract: An electroplating apparatus includes an electrode at the bottom of a chamber, an ionically resistive element with through holes arranged horizontally at the top of the chamber, with a membrane in the middle. One or more panels extend vertically and parallelly from the membrane to the element and extend linearly across the chamber, forming a plurality of regions between the membrane and the element. A substrate with a protuberance extending along a chord of the substrate and contacting a top surface of the element is arranged above a first region. An electrolyte flowed between the substrate and the element descends into the first region via the through holes on a first side of the protuberance and ascends from the first region via the through holes on a second side of the protuberance, forcing air bubbles out from a portion of the element associated with the first region.

Abstract: Methods and apparatus for determining whether a substrate includes an unacceptably high amount of oxide on its surface are described. The substrate is typically a substrate that is to be electroplated. The determination may be made directly in an electroplating apparatus, during an initial portion of an electroplating process. The determination may involve immersing the substrate in electrolyte with a particular applied voltage or applied current provided during or soon after immersion, and recording a current response or voltage response over this same timeframe. The applied current or applied voltage may be zero or non-zero. By comparing the current response or voltage response to a threshold current, threshold voltage, or threshold time, it can be determined whether the substrate included an unacceptably high amount of oxide on its surface. The threshold current, threshold voltage, and/or threshold time may be selected based on a calibration procedure.

Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

Abstract: Processing methods and apparatus for increasing a reaction chamber batch size. Such a method of processing deposition substrates (e.g., wafers), involves conducting a deposition on a first portion of a batch of deposition wafers in a reaction chamber, conducting an interval conditioning reaction chamber purge to remove defects generated by the wafer processing from the reaction chamber; and following the interval conditioning mid-batch reaction chamber purge, conducting the deposition on another portion of the batch of wafers in the reaction chamber. The interval conditioning reaction chamber purge is conducted prior to exceeding a baseline for acceptable defect (e.g., particle) generation in the chamber and is performed while no wafers are positioned in the reaction chamber.

Abstract: Imaging layers on the surface of a substrate may be patterned using next generation lithographic techniques, and the resulting patterned film may be used as a lithographic mask, for example, for production of a semiconductor device.

Abstract: The embodiments herein relate to apparatuses and methods for electroplating one or more materials onto a substrate. Embodiments herein utilize a cross flow conduit in the electroplating cell to divert flow of fluid from a region between a substrate and a channeled ionically resistive plate positioned near the substrate down to a level lower than level of fluid in a fluid containment unit for collecting overflow fluid from the plating system for recirculation. The cross flow conduit can include channels cut into components of the plating cell to allow diverted flow, or can include an attachable diversion device mountable to an existing plating cell to divert flow downwards to the fluid containment unit. Embodiments also include a flow restrictor which may be a plate or a pressure relief valve for modulating flow of fluid in the cross flow conduit during plating.

Abstract: Systems and methods for achieving a pre-determined factor associated with the edge region within the plasma chamber is described. One of the methods includes providing an RF signal to a main electrode within the plasma chamber. The RF signal is generated based on a frequency of operation of a first RF generator. The method further includes providing another RF signal to an edge electrode within the plasma chamber. The other RF signal is generated based on the frequency of operation of the first RF generator. The method includes receiving a first measurement of a variable, receiving a second measurement of the variable, and modifying a phase of the other RF signal based on the first measurement and the second measurement. The method includes changing a magnitude of a variable associated with a second RF generator to achieve the pre-determined factor.

Abstract: A method includes: receiving a first signal from a first sensor at a first filter and preventing passage of a first portion of the first signal via the first filter. The first portion of the first signal is at a first RF. A second portion of the first signal is indicative of a first temperature of a first electrode in a plasma chamber. The method further includes: outputting a second signal from the first filter; receiving the second signal at a second filter; and preventing passage of a portion of the second signal via the second filter. The portion of the second signal is at a second RF. The second RF is less than the first RF. The first filter and the second filter are implemented on a printed circuit board. The method further includes adjusting a temperature of the first electrode based on an output of the second filter.

Abstract: Disclosed are apparatuses and methods for providing a substrate onto a substrate support in a processing chamber, generating an inert plasma in the processing chamber, and maintaining the inert plasma to heat the substrate to a steady state temperature, suitable for conducting plasma-enhanced chemical vapor deposition (PECVD), in less than 30 seconds from providing the substrate onto the substrate support. An apparatus may include a processing chamber, a process station that includes a substrate support, a process gas unit configured to flow an inert gas onto a substrate supported by the substrate support, a plasma source configured to generate an inert plasma in the process station, and a controller with instructions configured to flow the inert gas onto the substrate, generate the inert plasma in the first process station, and maintain the inert plasma to thereby heat the substrate.

Abstract: Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.

Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.

Abstract: A substrate processing system for processing a substrate within a processing chamber is provided and includes a source terminal, a substrate support, and a tuning circuit. The substrate support holds the substrate and includes first and second electrodes, which receive power from a power source via the source terminal. The tuning circuit is connected to the first electrode or the second electrode. The tuning circuit is allocated for tuning signals provided to the first electrode. The tuning circuit includes at least one of a first impedance set or a second impedance set. The first impedance set is serially connected between the first electrode and the power source and receives a first signal from the power source via the source terminal. The second impedance set is connected between an output of the power source and a reference terminal and receives the first signal from the power source via the source terminal.

Abstract: A heater control system for heating components of a substrate processing system includes N heater zones, where N is an integer greater than zero. Each of the N heater zones heats a component of the substrate processing system and includes a resistive heater and a temperature sensor to sense a local temperature in a corresponding one of the N heater zones. A controller is configured to determine an average temperature of each of the N heater zones based on a resistance of the resistive heater in each of the N heater zones. The controller controls the resistive heater based on the average temperature and the local temperature in each of the N heater zones.

Abstract: Provided herein are methods and apparatus for characterizing high aspect ratio (HAR) structures of fabricated or partially fabricated semiconductor devices. The methods involve using small angle X-ray scattering (SAXS) to determine average parameters of an array of HAR structures. In some implementations, SAXS is used to analyze symmetry of HAR structures in a sample and may be referred to as tilted structural symmetry analysis-SAXS (TSSA-SAXS) or TSSA. Analysis of parameters such as tilt, sidewall angle, bowing, and the presence of multiple tilts in HAR structures may be performed.

Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

Abstract: In some examples, a magnetic shield for a plasma source is provided. An example magnetic shield comprises a back-shell. The back-shell includes a cage defined, at least in part, by an arrangement of bars of ferro-magnetic material. The cage is sized and configured to at least extend over a top side of an RF source coil for the plasma source.

Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

Abstract: A method of forming a feature in a stack comprising a dielectric material on a substrate is provided. An etch plasma is generated from an etch gas, exposing the stack to the etch plasma and partially etching the feature in the stack. The stack is primed. A protective film is deposited on sidewalls of the feature by repeating for a plurality of cycles the steps of exposing the stack to a first reactant, allowing the first reactant to adsorb onto the stack, and exposing the stack to a second reactant, wherein the first and second reactants react with one another to form the protective film over the stack. The etching, priming, and depositing a protective film are repeated until the feature is etched to a final depth.