Abstract: A method for making an integrated circuit includes a) providing a substrate including n-type metal oxide semiconductor field effect transistors (NMOSFETs) and p-type metal oxide semiconductor field effect transistors (PMOSFETs), wherein channel regions of the NMOSFETs and the PMOSFETs include germanium; b) depositing and patterning a mask layer to mask the channel regions of the PMOSFETs and to not mask the channel regions of the NMOSFETs; c) passivating an exposed surface of the substrate; d) removing the mask layer; and e) depositing a metal contact layer on both the NMOSFETs and the PMOSFETs.

Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.

Abstract: Methods of depositing tungsten in different sized features on a substrate are provided herein. The methods involve depositing a first bulk layer of tungsten in the features, etching the deposited tungsten, depositing a second bulk tungsten, which is interrupted to treat the tungsten after the smaller features are completely filled, and resuming deposition of the second bulk layer after treatment to deposit smaller, smoother tungsten grains into the large features. The methods also involve depositing tungsten in multiple cycles of dep-etch-dep, where each cycle targets a group of similarly sized features using etch chemistry specific for that group, and depositing in groups from smallest sized features to the largest sized features. Deposition using methods described herein produce smaller, smoother grains with void-free fill for a wide range of sized features in a substrate.

Abstract: A method of conditioning a vacuum chamber of a semiconductor substrate processing apparatus includes forming a layer of an organic polymeric film on plasma or process gas exposed surfaces thereof. The method includes: (a) flowing a first reactant in vapor phase of a diacyl chloride into the vacuum chamber; (b) purging the vacuum chamber after a flow of the first reactant has ceased; (c) flowing a second reactant in vapor phase into the vacuum chamber selected from the group consisting of a diamine, a diol, a thiol, and a trifunctional compound to form a layer of an organic polymeric film on the plasma or process gas exposed surfaces of the vacuum chamber; and (d) purging the vacuum chamber to purge excess second reactant and reaction byproducts from the vacuum chamber.

Abstract: A method of forming a dense oxide coating on an aluminum component of semiconductor processing equipment comprises cold spraying a layer of pure aluminum on a surface of the aluminum component to a predetermined thickness. A dense oxide coating is then formed on the layer of pure aluminum using a plasma electrolytic oxidation process, wherein the plasma electrolytic oxidation process causes the layer of pure aluminum to undergo microplasmic discharges, thus forming the dense oxide coating on the layer of pure aluminum on the surface of the aluminum component.

Abstract: A substrate etching system includes an etching control module, a filtering module, and an endpoint module. The etching control module selectively begins plasma etching of a substrate within an etching chamber. The filtering module, during the plasma etching of the substrate: receives a signal including endpoint information; decomposes the signal using empirical mode decomposition (EMD); and generates a filtered signal based on results of the EMD. The endpoint module indicates when an endpoint of the plasma etching of the substrate has been reached based on the filtered signal. The etching control module ends the plasma etching of the substrate in response to the indication that the endpoint of the plasma etching of the substrate has been reached.

Abstract: A plasma processing system having a plasma processing chamber configured for processing a substrate is provided. The plasma processing system includes at least an upper electrode and a lower electrode for processing the substrate. The substrate is disposed on the lower electrode during plasma processing, where the upper electrode and the substrate forms a first gap. The plasma processing system also includes an upper electrode peripheral extension (UE-PE). The UE-PE is mechanically coupled to a periphery of the upper electrode, where the UE-PE is configured to be non-coplanar with the upper electrode. The plasma processing system further includes a cover ring. The cover ring is configured to concentrically surround the lower electrode, where the UE-PE and the cover ring forms a second gap.

Abstract: A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with molecular hydrogen to create a hydrogen-doped outer layer; and nano-doping the hydrogen-doped outer layer using one of boron or phosphorous to a target junction depth to create a nano-doped layer.

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in substantial preservation of a mask layer on the substrate. The protective coating may be deposited using particular reactants and/or reaction conditions that are unlikely to damage the mask layer. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating.

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.

Abstract: A method for auto-correction of at least one malfunctioning thermal control element among an array of thermal control elements that are independently controllable and located in a temperature control plate of a substrate support assembly which supports a semiconductor substrate during processing thereof, the method including: detecting, by a control unit including a processor, that at least one thermal control element of the array of thermal control elements is malfunctioning; deactivating, by the control unit, the at least one malfunctioning thermal control element; and modifying, by the control unit, a power level of at least one functioning thermal control element in the temperature control plate to minimize impact of the malfunctioning thermal control element on the desired temperature output at the location of the at least one malfunctioning thermal control element.

Abstract: Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior region with a wafer receiving mechanism and a viewport disposed on a sidewall of the plasma processing chamber providing visual access from the exterior to the wafer received on the wafer receiving mechanism. A camera is mounted to the viewport of the plasma processing chamber on the exterior and coupled to an image processor. The image processor includes pattern recognition logic to match images of emerging pattern captured and transmitted by the camera, to a reference pattern and to generate signal defining an endpoint when a match is detected. A system process controller coupled to the image processor and the plasma processing chamber receives the signal from the image processor and adjusts controls of one or more resources to stop the etching operation.

Abstract: Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

Abstract: An end effector of a wafer transfer system includes synchronously movable blades operable to hold and release wafers. The end effector comprises an end effector housing including a first blade mount coupled to a first blade, a second blade mount coupled to a second blade, and an actuator operable to move the blade mounts on respective linear rails. The actuator includes a longitudinally movable piston coupled to the respective blade mounts by respective actuator links. The actuator links are pivotally coupled to the longitudinally movable piston at respective first ends thereof and to the first and second blade mounts at respective second ends thereof wherein moving the piston towards a retracted position causes the blades to synchronously move laterally towards each other and moving the piston towards the retracted position causes the blades to synchronously move laterally away from each other so as to hold or release a wafer.

Abstract: In a plasma processing chamber, a method for processing a substrate is provided. The method includes supporting the substrate in the plasma processing chamber configured with an upper electrode (UE) and a lower electrode (LE), configuring at least one radio frequency power source to ignite plasma between the UE and the LE, and providing a conductive coupling ring, the conductive coupling ring is coupled to the LE to provide a conductive path. The method further includes providing a plasma-facing-substrate-periphery (PFSP) ring, the PFSP ring being disposed above the conductive coupling ring. The method yet further includes coupling the PFSP ring to at least one of a direct current (DC) ground through an RF filter, the DC ground through the RF filter and a variable resistor, a positive DC power source through the RF filter, and a negative DC power source through the RF filter to control plasma processing parameters.

Abstract: A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a radio frequency (RF) pulse signal. The RF pulse signal includes a first state and a second state. The first state has a higher power level than the second state. The method further includes receiving a pulse slope associated with the RF pulse signal. The pulse slope provides a transition between the first state and the second state. Also, the pulse slope is other than substantially infinite for reducing an amount of ion energy during the etch operation. The method includes determining power levels and timings for achieving the pulse slope and sending the power levels and the timings to an RF generator to generate the RF pulse signal.

Abstract: A chuck includes a first material layer having an upper surface upon which a wafer is supported. The upper surface includes portions that physically contact the wafer and portions that form gaps between the upper surface and the wafer. The chuck also includes a second material layer defined to support the first material layer. The second material layer is formed of a thermally conductive material and includes a first number of channels. The chuck also includes a second number of channels defined to direct a gas to portions of the upper surface that form gaps between the upper surface and the wafer. The chuck is characterized by a thermal calibration curve that represents a thermal interface between the upper surface and the wafer, heat transfer through the first material layer to the second material layer, and heat transfer through the second material layer to the first number of channels.

Abstract: Systems, methods, and computer programs are presented for controlling the temperature of a window in a semiconductor manufacturing chamber. One apparatus includes an air amplifier, a plenum, a heater, a temperature sensor, and a controller. The air amplifier is coupled to pressurized gas and generates, when activated, a flow of air. The air amplifier is also coupled to the plenum and the heater. The plenum receives the flow of air and distributes the flow of air over a window of the plasma chamber. When the heater is activated, the flow of air is heated during processing, and when the heater is not activated, the flow of air cools the window. The temperature sensor is situated about the window of the plasma chamber, and the controller is defined to activate both the air amplifier and the heater based on a temperature measured by the temperature sensor.

Abstract: A method for processing a substrate in a process chamber is provided. A plurality of cycles is provided to process the substrate, wherein each cycle comprises the steps of providing a flow of a first process gas into the process chamber, stopping the flow of the first process gas into the process chamber, providing a flow of a first transition gas into the process chamber, wherein the first transition gas neutralizes a component of the first process gas, stopping the flow of the first transition gas into the process chamber, providing a flow of a second process gas into the process chamber, stopping the second process gas into the process chamber, and maintaining a continuous plasma during the cycle.

Abstract: Systems and methods for using variables based on a state associated with a plasma system. A method includes determining whether the state associated with the plasma system is a first state or a second state and determining a first variable upon determining that the state is the first state. The first variable is determined based on a measurement at a communication medium. The method further includes determining a second variable upon determining that the state is the second state. The second variable is determined based on a measurement at the communication medium. The method includes determining whether the second variable exceeds a first threshold, providing an instruction to reduce power supplied to a plasma chamber upon determining that the second variable exceeds the first threshold, and providing an instruction to increase power supplied to the plasma chamber upon determining that the second variable is below the first threshold.